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-rwxr-xr-xsrc/arch/isa_parser.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 6504c7b32..2086473d6 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1306,7 +1306,7 @@ class ControlRegOperand(Operand):
bit_select = 0
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to read control register as FP')
- base = 'xc->readMiscReg(%s)' % self.reg_spec
+ base = 'xc->readMiscRegWithEffect(%s)' % self.reg_spec
if self.size == self.dflt_size:
return '%s = %s;\n' % (self.base_name, base)
else: