diff options
Diffstat (limited to 'src/arch/isa_parser.py')
| -rwxr-xr-x | src/arch/isa_parser.py | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 7edb9f3d7..754a64fdb 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1414,6 +1414,28 @@ class ControlRegOperand(Operand): self.base_name return wb +class ControlBitfieldOperand(ControlRegOperand): + def makeRead(self): + bit_select = 0 + if (self.ctype == 'float' or self.ctype == 'double'): + error(0, 'Attempt to read control register as FP') + base = 'xc->readMiscReg(%s)' % self.reg_spec + name = self.base_name + return '%s = bits(%s, %s_HI, %s_LO);' % \ + (name, base, name, name) + + def makeWrite(self): + if (self.ctype == 'float' or self.ctype == 'double'): + error(0, 'Attempt to write control register as FP') + base = 'xc->readMiscReg(%s)' % self.reg_spec + name = self.base_name + wb_val = 'insertBits(%s, %s_HI, %s_LO, %s)' % \ + (base, name, name, self.base_name) + wb = 'xc->setMiscRegOperand(this, %s, %s );\n' % (self.dest_reg_idx, wb_val) + wb += 'if (traceData) { traceData->setData(%s); }' % \ + self.base_name + return wb + class MemOperand(Operand): def isMem(self): return 1 |