diff options
Diffstat (limited to 'src/arch/isa_parser.py')
| -rwxr-xr-x | src/arch/isa_parser.py | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index fb398d152..ef21f7ceb 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1414,6 +1414,43 @@ class ControlRegOperand(Operand): self.base_name return wb +class IControlRegOperand(Operand): + def isReg(self): + return 1 + + def isIControlReg(self): + return 1 + + def makeConstructor(self): + c = '' + if self.is_src: + c += '\n\t_srcRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \ + (self.src_reg_idx, self.reg_spec) + if self.is_dest: + c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \ + (self.dest_reg_idx, self.reg_spec) + return c + + def makeRead(self): + bit_select = 0 + if (self.ctype == 'float' or self.ctype == 'double'): + error(0, 'Attempt to read control register as FP') + base = 'xc->readMiscReg(%s)' % self.reg_spec + if self.size == self.dflt_size: + return '%s = %s;\n' % (self.base_name, base) + else: + return '%s = bits(%s, %d, 0);\n' % \ + (self.base_name, base, self.size-1) + + def makeWrite(self): + if (self.ctype == 'float' or self.ctype == 'double'): + error(0, 'Attempt to write control register as FP') + wb = 'xc->setMiscReg(%s, %s);\n' % \ + (self.reg_spec, self.base_name) + wb += 'if (traceData) { traceData->setData(%s); }' % \ + self.base_name + return wb + class ControlBitfieldOperand(ControlRegOperand): def makeRead(self): bit_select = 0 |