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-rw-r--r--src/arch/mips/MipsCPU.py5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/mips/MipsCPU.py b/src/arch/mips/MipsCPU.py
index 81c6bdacf..48ee4171c 100644
--- a/src/arch/mips/MipsCPU.py
+++ b/src/arch/mips/MipsCPU.py
@@ -29,12 +29,13 @@
# Authors: Jaidev Patwardhan
# Korey Sewell
-from m5.SimObject import SimObject
+from m5.defines import buildEnv
from m5.params import *
+
from BaseCPU import BaseCPU
class BaseMipsCPU(BaseCPU)
- if build_env['TARGET_ISA'] == 'mips':
+ if buildEnv['TARGET_ISA'] == 'mips':
CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")