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-rw-r--r--src/arch/mips/MipsTLB.py20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
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index 000000000..8c1a00abe
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+++ b/src/arch/mips/MipsTLB.py
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+from m5.SimObject import SimObject
+from m5.params import *
+class MipsTLB(SimObject):
+ type = 'MipsTLB'
+ abstract = True
+ #size = Param.Int("TLB size")
+
+class MipsDTB(MipsTLB):
+ type = 'MipsDTB'
+ cxx_namespace = 'MipsISA'
+ cxx_class = 'DTB'
+
+ #size = 64
+
+class MipsITB(MipsTLB):
+ type = 'MipsITB'
+ cxx_namespace = 'MipsISA'
+ cxx_class = 'ITB'
+
+ #size = 64