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-rw-r--r--src/arch/mips/MipsTLB.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index b2735d0e7..d06a0e7dd 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -39,19 +39,19 @@ class MipsTLB(SimObject):
size = Param.Int("TLB size")
class MipsDTB(MipsTLB):
- type = 'DTB'
+ type = 'MipsDTB'
cxx_namespace = 'MipsISA'
cxx_class = 'DTB'
size = 64
class MipsITB(MipsTLB):
- type = 'ITB'
+ type = 'MipsITB'
cxx_namespace = 'MipsISA'
cxx_class = 'ITB'
size = 64
class MipsUTB(MipsTLB):
- type = 'UTB'
+ type = 'MipsUTB'
cxx_namespace = 'MipsISA'
cxx_class = 'UTB'
size = 64