1 files changed, 64 insertions, 165 deletions

diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index 99f96fafc..4b1f37856 100755
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -31,243 +31,142 @@
  *          Korey Sewell
  */
 
-#include "arch/mips/pra_constants.hh"
+#include "arch/mips/interrupts.hh"
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/pra_constants.hh"
+#include "base/trace.hh"
 #include "cpu/thread_context.hh"
-#include "arch/mips/interrupts.hh"
 
 namespace MipsISA
 {
-static inline uint8_t getCauseIP_(ThreadContext *tc) {
-    MiscReg cause = tc->readMiscRegNoEffect(MipsISA::Cause);
-    uint8_t IP_ = bits(cause,Cause_IP7, Cause_IP0);
-    return IP_;
-}
 
-static inline void setCauseIP_(ThreadContext *tc, uint8_t val) {
-    MiscReg cause = tc->readMiscRegNoEffect(MipsISA::Cause);
-    replaceBits(cause,Cause_IP7,Cause_IP0,val);
-    tc->setMiscRegNoEffect(MipsISA::Cause,cause);
+static inline uint8_t
+getCauseIP(ThreadContext *tc) {
+    CauseReg cause = tc->readMiscRegNoEffect(Cause);
+    return cause.ip;
 }
 
-/*
-  void Interrupts::post(int int_num, int index)
-  {
-  DPRINTF(Interrupt, "Interrupt %d posted\n", int_num);
-
-  //index should not be used
-  assert(index == 0);
-
-  if (int_num < 0 || int_num >= NumInterruptLevels)
-  panic("int_num out of bounds\n");
-  intstatus |= 1 << int_num;
-  }
-
-  void Interrupts::clear(int int_num, int index)
-  {
-  DPRINTF(Interrupt, "Interrupt %d cleared\n", int_num);
-
-  //index should not be used
-  assert(index == 0);
-
-  if (int_num < 0 || int_num >= NumInterruptLevels)
-  panic("int_num out of bounds\n");
-
-  intstatus &= ~(1 << int_num);
-  }
-
-  void Interrupts::clearAll()
-  {
-  DPRINTF(Interrupt, "Interrupts all cleared\n");
-  intstatus = 0;
-  }
-
-
-
-  Fault Interrupts::getInterrupt(ThreadContext * tc)
-  {
-  DPRINTF(Interrupt, "Interrupts getInterrupt\n");
-  // If a timer interrupt has occured, check to see if a
-  // mtc0 to Compare register caused this interrupt to
-  // be cleared. If this is the case, clear intstatus
-  // bit for timer interrupt
-  if (oncputimerintr){
-  DPRINTF(Interrupt, "Interrupts oncputimerintr==true\n");
-  MiscReg cause = tc->readMiscRegNoEffect(MipsISA::Cause);
-  uint8_t IP_ = bits(cause,Cause_IP7, Cause_IP0);
-  MiscReg intctl = tc->readMiscRegNoEffect(MipsISA::IntCtl);
-  uint8_t IPTI = bits(intctl, IntCtl_IPTI_HI, IntCtl_IPTI_LO);
-  //mtc0 to compare must have cleared bit in IP
-  if ( ((1 << IPTI) & IP_) == 0){
-  clear(IPTI, 0);
-  oncputimerintr=false;
-  }
-  }
-  //if there is a on cpu timer interrupt (i.e. Compare == Count)
-  //update intstatus before proceeding to interrupt
-  if (onCpuTimerInterrupt(tc)){
-  DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc)==true\n");
-  //determine timer interrupt IP #
-  MiscReg intctl = tc->readMiscRegNoEffect(MipsISA::IntCtl);
-  uint8_t IPTI = bits(intctl, IntCtl_IPTI_HI, IntCtl_IPTI_LO);
-  //set intstatus to correspond
-  post(IPTI, 0);
-  oncputimerintr=true;
-  }
-
-  //Check if there are any outstanding interrupts
-  MiscReg status = tc->readMiscRegNoEffect(MipsISA::Status);
-  if (bits(status, Status_IE_LO) == 1 && //interrupts must be enabled
-  bits(status, Status_ERL) == 0 &&  //error level must be 0 or interrupts inhibited
-  bits(status, Status_EXL) == 0 ) //exception level must be 0 or interrupts inhibited
-  {
-  // Software interrupts & hardware interrupts are handled in software.
-  // So if any interrupt that isn't masked is detected, jump to interrupt
-  // handler
-  uint8_t IM, IP; //IM=interrupt mask, IP=interrupt pending
-  IM = bits(status,Status_IM7,Status_IM0);
-  IP = intstatus;
-  //IM and IP are already correctly aligned
-  if (IM & IP){
-  DPRINTF(Flow, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
-  IM, IP);
-  return new InterruptFault;
-  }
-  }
-
-  return NoFault;
-
-  }
-
-  void Interrupts::updateIntrInfo(ThreadContext *tc) const
-  {
-  //Merge Interrupts.intstatus with mips MipISA::Status
-  MiscReg cause = tc->readMiscRegNoEffect(MipsISA::Cause);
-  replaceBits(cause,Cause_IP7,Cause_IP0,intstatus);
-  tc->setMiscRegNoEffect(MipsISA::Cause,cause);
-  }
-
-  bool Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
-  {
-  MiscReg compare = tc->readMiscRegNoEffect(MipsISA::Compare);
-  MiscReg count = tc->readMiscRegNoEffect(MipsISA::Count);
-  if (compare == count)
-  return true;
-  return false;
-  }
+static inline void
+setCauseIP(ThreadContext *tc, uint8_t val) {
+    CauseReg cause = tc->readMiscRegNoEffect(Cause);
+    cause.ip = val;
+    tc->setMiscRegNoEffect(Cause, cause);
+}
 
-*/
-void Interrupts::post(int int_num, ThreadContext* tc)
+void
+Interrupts::post(int int_num, ThreadContext* tc)
 {
     DPRINTF(Interrupt, "Interrupt %d posted\n", int_num);
     if (int_num < 0 || int_num >= NumInterruptLevels)
         panic("int_num out of bounds\n");
 
-    uint8_t intstatus= getCauseIP_(tc);
+    uint8_t intstatus = getCauseIP(tc);
     intstatus |= 1 << int_num;
-    setCauseIP_(tc, intstatus);
+    setCauseIP(tc, intstatus);
 }
 
-void Interrupts::post(int int_num, int index)
+void
+Interrupts::post(int int_num, int index)
 {
-    fatal("Must use Thread COntext when posting MIPS Interrupts in M5");
+    fatal("Must use Thread Context when posting MIPS Interrupts in M5");
 }
 
-void Interrupts::clear(int int_num, ThreadContext* tc)
+void
+Interrupts::clear(int int_num, ThreadContext* tc)
 {
     DPRINTF(Interrupt, "Interrupt %d cleared\n", int_num);
     if (int_num < 0 || int_num >= NumInterruptLevels)
         panic("int_num out of bounds\n");
 
-    uint8_t intstatus = getCauseIP_(tc);
+    uint8_t intstatus = getCauseIP(tc);
     intstatus &= ~(1 << int_num);
-    setCauseIP_(tc, intstatus);
+    setCauseIP(tc, intstatus);
 }
 
-void Interrupts::clear(int int_num, int index)
+void
+Interrupts::clear(int int_num, int index)
 {
-    fatal("Must use Thread COntext when clearing MIPS Interrupts in M5");
+    fatal("Must use Thread Context when clearing MIPS Interrupts in M5");
 }
 
-void Interrupts::clearAll(ThreadContext *tc)
+void
+Interrupts::clearAll(ThreadContext *tc)
 {
     DPRINTF(Interrupt, "Interrupts all cleared\n");
     uint8_t intstatus = 0;
-    setCauseIP_(tc, intstatus);
+    setCauseIP(tc, intstatus);
 }
 
-void Interrupts::clearAll()
+void
+Interrupts::clearAll()
 {
-    fatal("Must use Thread COntext when clearing MIPS Interrupts in M5");
+    fatal("Must use Thread Context when clearing MIPS Interrupts in M5");
 }
 
 
 
-Fault Interrupts::getInterrupt(ThreadContext * tc)
+Fault
+Interrupts::getInterrupt(ThreadContext * tc)
 {
     DPRINTF(Interrupt, "Interrupts getInterrupt\n");
 
-
-
     //Check if there are any outstanding interrupts
-    MiscReg status = tc->readMiscRegNoEffect(MipsISA::Status);
-    if (bits(status, Status_IE_LO) == 1 && //interrupts must be enabled
-        bits(status, Status_ERL_HI,Status_ERL_LO) == 0 &&  //error level must be 0 or interrupts inhibited
-        bits(status, Status_EXL_HI,Status_EXL_LO) == 0 ) //exception level must be 0 or interrupts inhibited
-    {
+    StatusReg status = tc->readMiscRegNoEffect(Status);
+    // Interrupts must be enabled, error level must be 0 or interrupts
+    // inhibited, and exception level must be 0 or interrupts inhibited
+    if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
         // Software interrupts & hardware interrupts are handled in software.
         // So if any interrupt that isn't masked is detected, jump to interrupt
         // handler
-        uint8_t IM, IP; //IM=interrupt mask, IP=interrupt pending
-        IM = bits(status,Status_IM7,Status_IM0);
-        IP = getCauseIP_(tc);
-        //IM and IP are already correctly aligned
-        if (IM & IP){
+        CauseReg cause = tc->readMiscRegNoEffect(Cause);
+        if (status.im && cause.ip) {
             DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
-                    IM, IP);
+                    (unsigned)status.im, (unsigned)cause.ip);
             return new InterruptFault;
         }
     }
 
     return NoFault;
-
 }
-bool Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
+
+bool
+Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
 {
-    MiscReg compare = tc->readMiscRegNoEffect(MipsISA::Compare);
-    MiscReg count = tc->readMiscRegNoEffect(MipsISA::Count);
+    MiscReg compare = tc->readMiscRegNoEffect(Compare);
+    MiscReg count = tc->readMiscRegNoEffect(Count);
     if (compare == count && count != 0)
         return true;
     return false;
 }
-void Interrupts::updateIntrInfo(ThreadContext *tc) const
+
+void
+Interrupts::updateIntrInfo(ThreadContext *tc) const
 {
     //Nothing needs to be done.
-    ;
 }
 
-bool Interrupts::interruptsPending(ThreadContext *tc) const
+bool
+Interrupts::interruptsPending(ThreadContext *tc) const
 {
     //if there is a on cpu timer interrupt (i.e. Compare == Count)
     //update CauseIP before proceeding to interrupt
-    if (onCpuTimerInterrupt(tc)){
-        DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc)==true\n");
+    if (onCpuTimerInterrupt(tc)) {
+        DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");
         //determine timer interrupt IP #
-        MiscReg intctl = tc->readMiscRegNoEffect(MipsISA::IntCtl);
-        uint8_t IPTI = bits(intctl, IntCtl_IPTI_HI, IntCtl_IPTI_LO);
-        //set intstatus to correspond
-        //post(IPTI, tc);
-        uint8_t intstatus= getCauseIP_(tc);
-        intstatus |= 1 << IPTI;
-        setCauseIP_(tc, intstatus);
+        IntCtlReg intCtl = tc->readMiscRegNoEffect(IntCtl);
+        uint8_t intStatus = getCauseIP(tc);
+        intStatus |= 1 << intCtl.ipti;
+        setCauseIP(tc, intStatus);
     }
 
-    return (getCauseIP_(tc) != 0);
+    return (getCauseIP(tc) != 0);
 
 }
 
+}
 
-
-
-
+MipsISA::Interrupts *
+MipsInterruptsParams::create()
+{
+    return new MipsISA::Interrupts(this);
 }