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Diffstat (limited to 'src/arch/mips/interrupts.hh')
-rwxr-xr-xsrc/arch/mips/interrupts.hh28
1 files changed, 15 insertions, 13 deletions
diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh
index 99a8f6fa0..af71e4636 100755
--- a/src/arch/mips/interrupts.hh
+++ b/src/arch/mips/interrupts.hh
@@ -57,23 +57,23 @@ class Interrupts
// for posting an interrupt. It sets a bit
// in intstatus corresponding to Cause IP*. The
// MIPS register Cause is updated by updateIntrInfo
- // which is called by check_interrupts
+ // which is called by checkInterrupts
//
void post(int int_num, int index);
// clear(int int_num, int index) is responsible
// for clearing an interrupt. It clear a bit
// in intstatus corresponding to Cause IP*. The
// MIPS register Cause is updated by updateIntrInfo
- // which is called by check_interrupts
+ // which is called by checkInterrupts
//
void clear(int int_num, int index);
- // clear_all() is responsible
+ // clearAll() is responsible
// for clearing all interrupts. It clears all bits
// in intstatus corresponding to Cause IP*. The
// MIPS register Cause is updated by updateIntrInfo
- // which is called by check_interrupts
+ // which is called by checkInterrupts
//
- void clear_all();
+ void clearAll();
// getInterrupt(ThreadContext * tc) checks if an interrupt
// should be returned. It ands the interrupt mask and
@@ -91,7 +91,7 @@ class Interrupts
void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
bool onCpuTimerInterrupt(ThreadContext *tc) const;
- bool check_interrupts(ThreadContext * tc) const{
+ bool checkInterrupts(ThreadContext *tc) const {
//return (intstatus != 0) && !(tc->readPC() & 0x3);
if (oncputimerintr == false){
updateIntrInfo(tc);
@@ -119,7 +119,7 @@ class Interrupts
// for posting an interrupt. It sets a bit
// in intstatus corresponding to Cause IP*. The
// MIPS register Cause is updated by updateIntrInfo
- // which is called by check_interrupts
+ // which is called by checkInterrupts
//
void post(int int_num, ThreadContext* tc);
void post(int int_num, int index);
@@ -128,19 +128,19 @@ class Interrupts
// for clearing an interrupt. It clear a bit
// in intstatus corresponding to Cause IP*. The
// MIPS register Cause is updated by updateIntrInfo
- // which is called by check_interrupts
+ // which is called by checkInterrupts
//
void clear(int int_num, ThreadContext* tc);
void clear(int int_num, int index);
- // clear_all() is responsible
+ // clearAll() is responsible
// for clearing all interrupts. It clears all bits
// in intstatus corresponding to Cause IP*. The
// MIPS register Cause is updated by updateIntrInfo
- // which is called by check_interrupts
+ // which is called by checkInterrupts
//
- void clear_all(ThreadContext* tc);
- void clear_all();
+ void clearAll(ThreadContext* tc);
+ void clearAll();
// getInterrupt(ThreadContext * tc) checks if an interrupt
// should be returned. It ands the interrupt mask and
@@ -158,7 +158,9 @@ class Interrupts
bool interruptsPending(ThreadContext *tc) const;
bool onCpuTimerInterrupt(ThreadContext *tc) const;
- bool check_interrupts(ThreadContext * tc) const{
+ bool
+ checkInterrupts(ThreadContext *tc) const
+ {
return interruptsPending(tc);
}