diff options
Diffstat (limited to 'src/arch/mips/isa.hh')
| -rw-r--r-- | src/arch/mips/isa.hh | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh index cea2d5412..2055fb059 100644 --- a/src/arch/mips/isa.hh +++ b/src/arch/mips/isa.hh @@ -68,8 +68,8 @@ namespace MipsISA perVirtProcessor }; - std::vector<std::vector<MiscReg> > miscRegFile; - std::vector<std::vector<MiscReg> > miscRegFile_WriteMask; + std::vector<std::vector<RegVal> > miscRegFile; + std::vector<std::vector<RegVal> > miscRegFile_WriteMask; std::vector<BankType> bankType; public: @@ -88,18 +88,17 @@ namespace MipsISA //@TODO: MIPS MT's register view automatically connects // Status to TCStatus depending on current thread void updateCP0ReadView(int misc_reg, ThreadID tid) { } - MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; + RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; //template <class TC> - MiscReg readMiscReg(int misc_reg, - ThreadContext *tc, ThreadID tid = 0); + RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); - MiscReg filterCP0Write(int misc_reg, int reg_sel, MiscReg val); - void setRegMask(int misc_reg, MiscReg val, ThreadID tid = 0); - void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0); + RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val); + void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0); + void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0); //template <class TC> - void setMiscReg(int misc_reg, MiscReg val, + void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid=0); ////////////////////////////////////////////////////////// |