diff options
Diffstat (limited to 'src/arch/mips/isa/formats/control.isa')
| -rw-r--r-- | src/arch/mips/isa/formats/control.isa | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa index 1480a5589..c9ef6707f 100644 --- a/src/arch/mips/isa/formats/control.isa +++ b/src/arch/mips/isa/formats/control.isa @@ -80,7 +80,7 @@ output header {{ // Basic instruction class execute method template. def template CP0Execute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; %(op_decl)s; @@ -101,7 +101,7 @@ def template CP0Execute {{ }}; def template CP1Execute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; %(op_decl)s; @@ -122,7 +122,7 @@ def template CP1Execute {{ }}; // Basic instruction class execute method template. def template ControlTLBExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; %(op_decl)s; @@ -181,7 +181,7 @@ output header {{ output exec {{ bool - isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num) + isCoprocessorEnabled(CPU_EXEC_CONTEXT *xc, unsigned cop_num) { if (!FullSystem) return true; @@ -203,7 +203,7 @@ output exec {{ } bool inline - isCoprocessor0Enabled(%(CPU_exec_context)s *xc) + isCoprocessor0Enabled(CPU_EXEC_CONTEXT *xc) { if (FullSystem) { MiscReg Stat = xc->readMiscReg(MISCREG_STATUS); @@ -219,7 +219,7 @@ output exec {{ } bool - isMMUTLB(%(CPU_exec_context)s *xc) + isMMUTLB(CPU_EXEC_CONTEXT *xc) { MiscReg Config = xc->readMiscReg(MISCREG_CONFIG); return FullSystem && (Config & 0x380) == 0x80; |