diff options
Diffstat (limited to 'src/arch/mips/isa/formats/fp.isa')
| -rw-r--r-- | src/arch/mips/isa/formats/fp.isa | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index c0dff477b..eb5e5765a 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -87,12 +87,12 @@ output decoder {{ }}; output header {{ - void fpResetCauseBits(%(CPU_exec_context)s *cpu); + void fpResetCauseBits(ExecContext *cpu); }}; output exec {{ - inline Fault checkFpEnableFault(CPU_EXEC_CONTEXT *xc) + inline Fault checkFpEnableFault(ExecContext *xc) { //@TODO: Implement correct CP0 checks to see if the CP1 // unit is enable or not @@ -105,7 +105,7 @@ output exec {{ //If any operand is Nan return the appropriate QNaN template <class T> bool - fpNanOperands(FPOp *inst, CPU_EXEC_CONTEXT *xc, const T &src_type, + fpNanOperands(FPOp *inst, ExecContext *xc, const T &src_type, Trace::InstRecord *traceData) { uint64_t mips_nan = 0; @@ -126,7 +126,7 @@ output exec {{ template <class T> bool - fpInvalidOp(FPOp *inst, CPU_EXEC_CONTEXT *cpu, const T dest_val, + fpInvalidOp(FPOp *inst, ExecContext *cpu, const T dest_val, Trace::InstRecord *traceData) { uint64_t mips_nan = 0; @@ -156,7 +156,7 @@ output exec {{ } void - fpResetCauseBits(CPU_EXEC_CONTEXT *cpu) + fpResetCauseBits(ExecContext *cpu) { //Read FCSR from FloatRegFile uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); @@ -170,7 +170,8 @@ output exec {{ }}; def template FloatingPointExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; |