diff options
Diffstat (limited to 'src/arch/mips/isa/formats/fp.isa')
| -rw-r--r-- | src/arch/mips/isa/formats/fp.isa | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index 52fcd0724..72d87f997 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -135,12 +135,13 @@ output exec {{ cpu->setFloatRegOperandBits(inst, 0, mips_nan); //Read FCSR from FloatRegFile - uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); + uint32_t fcsr_bits = + cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); uint32_t new_fcsr = genInvalidVector(fcsr_bits); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr); + cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr); if (traceData) { traceData->setData(mips_nan); } return true; @@ -153,13 +154,13 @@ output exec {{ fpResetCauseBits(%(CPU_exec_context)s *cpu) { //Read FCSR from FloatRegFile - uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR); + uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); // TODO: Use utility function here fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FCSR, fcsr); + cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr); } }}; |