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-rw-r--r--src/arch/mips/isa/formats/basic.isa5
-rw-r--r--src/arch/mips/isa/formats/branch.isa160
-rw-r--r--src/arch/mips/isa/formats/control.isa128
-rw-r--r--src/arch/mips/isa/formats/formats.isa7
-rw-r--r--src/arch/mips/isa/formats/fp.isa336
-rw-r--r--src/arch/mips/isa/formats/int.isa155
-rw-r--r--src/arch/mips/isa/formats/mem.isa130
-rw-r--r--src/arch/mips/isa/formats/mt.isa53
-rw-r--r--src/arch/mips/isa/formats/noop.isa8
-rw-r--r--src/arch/mips/isa/formats/tlbop.isa7
-rw-r--r--src/arch/mips/isa/formats/trap.isa15
-rw-r--r--src/arch/mips/isa/formats/unimp.isa38
-rw-r--r--src/arch/mips/isa/formats/unknown.isa39
-rw-r--r--src/arch/mips/isa/formats/util.isa25
14 files changed, 822 insertions, 284 deletions
diff --git a/src/arch/mips/isa/formats/basic.isa b/src/arch/mips/isa/formats/basic.isa
index c02af7ddc..e6c53d490 100644
--- a/src/arch/mips/isa/formats/basic.isa
+++ b/src/arch/mips/isa/formats/basic.isa
@@ -12,11 +12,11 @@ def template BasicDeclare {{
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ public:
/// Constructor.
%(class_name)s(MachInst machInst);
%(BasicExecDeclare)s
- };
+ };
}};
// Basic instruction class constructor template.
@@ -27,6 +27,7 @@ def template BasicConstructor {{
}
}};
+
// Basic instruction class execute method template.
def template BasicExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 8cfa37a20..e8843da03 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -68,29 +68,6 @@ output header {{
};
/**
- * Base class for branch likely branches (PC-relative control transfers),
- */
- class BranchLikely : public PCDependentDisassembly
- {
- protected:
- /// target address (signed) Displacement .
- int32_t disp;
-
- /// Constructor.
- BranchLikely(const char *mnem, MachInst _machInst, OpClass __opClass)
- : PCDependentDisassembly(mnem, _machInst, __opClass),
- disp(OFFSET << 2)
- {
-
- }
-
- Addr branchTarget(Addr branchPC) const;
-
- std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
-
- /**
* Base class for jumps (register-indirect control transfers). In
* the Mips ISA, these are always unconditional.
*/
@@ -111,7 +88,7 @@ output header {{
{
}
- Addr branchTarget(ExecContext *xc) const;
+ Addr branchTarget(ThreadContext *tc) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -126,16 +103,10 @@ output decoder {{
}
Addr
- BranchLikely::branchTarget(Addr branchPC) const
+ Jump::branchTarget(ThreadContext *tc) const
{
- return branchPC + 4 + disp;
- }
-
- Addr
- Jump::branchTarget(ExecContext *xc) const
- {
- Addr NPC = xc->readPC() + 4;
- uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
+ Addr NPC = tc->readPC() + 4;
+ uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
return (Rb & ~3) | (NPC & 1);
}
@@ -171,49 +142,12 @@ output decoder {{
// unconditional branches)
if (_numSrcRegs == 1) {
printReg(ss, _srcRegIdx[0]);
- ss << ",";
+ ss << ", ";
} else if(_numSrcRegs == 2) {
printReg(ss, _srcRegIdx[0]);
- ss << ",";
+ ss << ", ";
printReg(ss, _srcRegIdx[1]);
- ss << ",";
- }
-
- Addr target = pc + 4 + disp;
-
- std::string str;
- if (symtab && symtab->findSymbol(target, str))
- ss << str;
- else
- ccprintf(ss, "0x%x", target);
-
- string inst_name = mnemonic;
-
- if (inst_name.substr(inst_name.length()-2,inst_name.length()) == "al"){
- ccprintf(ss, " (r31=0x%x)",pc+8);
- }
-
- return ss.str();
- }
-
- std::string
- BranchLikely::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
-
- ccprintf(ss, "%-10s ", mnemonic);
-
- // There's only one register arg (RA), but it could be
- // either a source (the condition for conditional
- // branches) or a destination (the link reg for
- // unconditional branches)
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
- ss << ",";
- }
- else if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
- ss << ",";
+ ss << ", ";
}
Addr target = pc + 4 + disp;
@@ -247,72 +181,64 @@ output decoder {{
printReg(ss, _srcRegIdx[0]);
} else if(_numSrcRegs == 2) {
printReg(ss, _srcRegIdx[0]);
- ss << ",";
+ ss << ", ";
printReg(ss, _srcRegIdx[1]);
- } else {
- panic(">= 3 Source Registers!!!");
}
return ss.str();
}
}};
-def format Branch(code,*flags) {{
- #Add Link Code if Link instruction
- strlen = len(name)
- if name[strlen-2:] == 'al':
- code += 'R31 = NNPC;\n'
+def format Branch(code,*opt_flags) {{
+ not_taken_code = ' NNPC = NNPC;\n'
+ not_taken_code += '} \n'
+
+ #Build Instruction Flags
+ #Use Link & Likely Flags to Add Link/Condition Code
+ inst_flags = ('IsDirectControl', )
+ for x in opt_flags:
+ if x == 'Link':
+ code += 'R31 = NNPC;\n'
+ elif x == 'Likely':
+ not_taken_code = ' NPC = NNPC;\n'
+ not_taken_code += ' NNPC = NNPC + 4;\n'
+ not_taken_code += '} \n'
+ inst_flags = ('IsCondDelaySlot', )
+ else:
+ inst_flags += (x, )
+
+ if 'cond == 1' in code:
+ inst_flags += ('IsCondControl', )
+ else:
+ inst_flags += ('IsUncondControl', )
#Condition code
code = 'bool cond;\n' + code
code += 'if (cond) {\n'
code += ' NNPC = NPC + disp;\n'
code += '} else {\n'
- code += ' NNPC = NNPC;\n'
- code += '} \n'
-
- iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
- ('IsDirectControl', 'IsCondControl'))
+ code += not_taken_code
+ iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), inst_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
-
-def format BranchLikely(code,*flags) {{
- #Add Link Code if Link instruction
- strlen = len(name)
- if name[strlen-3:] == 'all':
- code += 'R31 = NNPC;\n'
-
- #Condition code
- code = 'bool cond;\n' + code
- code += 'if (cond) {'
- code += 'NNPC = NPC + disp;\n'
- code += '} \n'
-
-
- iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
- ('IsDirectControl', 'IsCondControl','IsCondDelaySlot'))
-
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
-}};
-
-def format Jump(code,*flags) {{
- #Add Link Code if Link instruction
- strlen = len(name)
- if strlen > 1 and name[1:] == 'al':
+def format Jump(code, *opt_flags) {{
+ #Build Instruction Flags
+ #Use Link Flag to Add Link Code
+ inst_flags = ('IsIndirectControl', 'IsUncondControl')
+ for x in opt_flags:
+ if x == 'Link':
code = 'R31 = NNPC;\n' + code
+ elif x == 'ClearHazards':
+ code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
+ else:
+ inst_flags += (x, )
-
- iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\
- ('IsIndirectControl', 'IsUncondControl'))
-
+ iop = InstObjParams(name, Name, 'Jump', CodeBlock(code), inst_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
new file mode 100644
index 000000000..f2f69d63c
--- /dev/null
+++ b/src/arch/mips/isa/formats/control.isa
@@ -0,0 +1,128 @@
+// -*- mode:c++ -*-
+
+////////////////////////////////////////////////////////////////////
+//
+// Integer operate instructions
+//
+
+//Outputs to decoder.hh
+output header {{
+
+ class Control : public MipsStaticInst
+ {
+ protected:
+
+ /// Constructor
+ Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ MipsStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ class CP0Control : public Control
+ {
+ protected:
+
+ /// Constructor
+ CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ Control(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ class CP1Control : public Control
+ {
+ protected:
+
+ /// Constructor
+ CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ Control(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+}};
+
+//Outputs to decoder.cc
+output decoder {{
+ std::string Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ if (mnemonic == "mfc0" || mnemonic == "mtc0") {
+ ccprintf(ss, "%-10s %d,%d,%d", mnemonic,RT,RD,SEL);
+ } else {
+
+ // just print the first dest... if there's a second one,
+ // it's generally implicit
+ if (_numDestRegs > 0) {
+ printReg(ss, _destRegIdx[0]);
+ }
+
+ ss << ", ";
+
+ // just print the first two source regs... if there's
+ // a third one, it's a read-modify-write dest (Rc),
+ // e.g. for CMOVxx
+ if (_numSrcRegs > 0) {
+ printReg(ss, _srcRegIdx[0]);
+ }
+
+ if (_numSrcRegs > 1) {
+ ss << ", ";
+ printReg(ss, _srcRegIdx[1]);
+ }
+ }
+
+ return ss.str();
+ }
+
+ std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+ ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
+ return ss.str();
+ }
+
+ std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+ ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
+ return ss.str();
+ }
+
+}};
+
+def format System(code, *flags) {{
+ iop = InstObjParams(name, Name, 'Control', CodeBlock(code), flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+def format CP0Control(code, *flags) {{
+ iop = InstObjParams(name, Name, 'CP0Control', CodeBlock(code), flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+def format CP1Control(code, *flags) {{
+ iop = InstObjParams(name, Name, 'CP1Control', CodeBlock(code), flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+
diff --git a/src/arch/mips/isa/formats/formats.isa b/src/arch/mips/isa/formats/formats.isa
index 7d493ffae..ed31788a6 100644
--- a/src/arch/mips/isa/formats/formats.isa
+++ b/src/arch/mips/isa/formats/formats.isa
@@ -10,8 +10,8 @@
//Include utility functions
##include "util.isa"
-//Include the cop0 formats
-##include "cop0.isa"
+//Include the control/cp0/cp1 formats
+##include "control.isa"
//Include the integer formats
##include "int.isa"
@@ -22,6 +22,9 @@
//Include the mem format
##include "mem.isa"
+//Include the mem format
+##include "mt.isa"
+
//Include the trap format
##include "trap.isa"
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 9f2c24755..1803c0e73 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -18,49 +18,264 @@ output header {{
{
}
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+ //needs function to check for fpEnable or not
+ };
+
+ class FPCompareOp : public FPOp
+ {
+ protected:
+ FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
};
}};
output decoder {{
- std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
- return "Disassembly of integer instruction\n";
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ ccprintf(ss,"%d",CC);
+
+ if(_numSrcRegs > 0) {
+ ss << ", ";
+ printReg(ss, _srcRegIdx[0]);
+ }
+
+ if(_numSrcRegs > 1) {
+ ss << ", ";
+ printReg(ss, _srcRegIdx[1]);
+ }
+
+ return ss.str();
}
}};
+output exec {{
-// Primary format for float operate instructions:
-def format FloatOp(code, *flags) {{
- iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
+ //If any operand is Nan return the appropriate QNaN
+ template <class T>
+ bool
+ fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
+ Trace::InstRecord *traceData)
+ {
+ uint64_t mips_nan = 0;
+ T src_op = 0;
+ int size = sizeof(src_op) * 8;
+
+ for (int i = 0; i < inst->numSrcRegs(); i++) {
+ uint64_t src_bits = xc->readFloatRegBits(inst, 0, size);
+
+ if (isNan(&src_bits, size) ) {
+ if (isSnan(&src_bits, size)) {
+ switch (size)
+ {
+ case 32: mips_nan = MIPS32_QNAN; break;
+ case 64: mips_nan = MIPS64_QNAN; break;
+ default: panic("Unsupported Floating Point Size (%d)", size);
+ }
+ } else {
+ mips_nan = src_bits;
+ }
+
+ xc->setFloatRegBits(inst, 0, mips_nan, size);
+ if (traceData) { traceData->setData(mips_nan); }
+ return true;
+ }
+ }
+ return false;
+ }
+
+ template <class T>
+ bool
+ fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
+ Trace::InstRecord *traceData)
+ {
+ uint64_t mips_nan = 0;
+ T src_op = dest_val;
+ int size = sizeof(src_op) * 8;
+
+ if (isNan(&src_op, size)) {
+ switch (size)
+ {
+ case 32: mips_nan = MIPS32_QNAN; break;
+ case 64: mips_nan = MIPS64_QNAN; break;
+ default: panic("Unsupported Floating Point Size (%d)", size);
+ }
+
+ //Set value to QNAN
+ cpu->setFloatRegBits(inst, 0, mips_nan, size);
+
+ //Read FCSR from FloatRegFile
+ uint32_t fcsr_bits = cpu->tc->readFloatRegBits(FCSR);
+
+ //Write FCSR from FloatRegFile
+ cpu->tc->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
+
+ if (traceData) { traceData->setData(mips_nan); }
+ return true;
+ }
+
+ return false;
+ }
+
+ void
+ fpResetCauseBits(%(CPU_exec_context)s *cpu)
+ {
+ //Read FCSR from FloatRegFile
+ uint32_t fcsr = cpu->tc->readFloatRegBits(FCSR);
+
+ fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
+
+ //Write FCSR from FloatRegFile
+ cpu->tc->setFloatRegBits(FCSR, fcsr);
+ }
}};
-def format FloatCompareOp(code, *flags) {{
- code = 'bool cond;\n' + code
- code += 'FCSR = makeCCVector(FCSR, CC,cond);\n'
- iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
+def template FloatingPointExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+
+ //When is the right time to reset cause bits?
+ //start of every instruction or every cycle?
+ fpResetCauseBits(xc);
+
+ %(op_decl)s;
+ %(op_rd)s;
+
+ //Check if any FP operand is a NaN value
+ if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
+ %(code)s;
+
+ //Change this code for Full-System/Sycall Emulation
+ //separation
+ //----
+ //Should Full System-Mode throw a fault here?
+ //----
+ //Check for IEEE 754 FP Exceptions
+ //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
+ if (!fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
+ fault == NoFault)
+ {
+ %(op_wb)s;
+ }
+ }
+
+ return fault;
+ }
}};
-def format FloatCompareWithXcptOp(code, *flags) {{
- code = 'bool cond;\n' + code
- code += 'FCSR = makeCCVector(FCSR, CC,cond);\n'
- iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+// Primary format for float point operate instructions:
+def format FloatOp(code, *flags) {{
+ iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
+ exec_output = FloatingPointExecute.subst(iop)
+}};
+
+def format FloatCompareOp(cond_code, *flags) {{
+ import sys
+
+ code = 'bool cond;\n'
+ if '.sf' in cond_code or 'SinglePrecision' in flags:
+ if 'QnanException' in flags:
+ code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n'
+ code += '\tFCSR = genInvalidVector(FCSR);\n'
+ code += '\treturn NoFault;'
+ code += '}\n else '
+ code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n'
+ elif '.df' in cond_code or 'DoublePrecision' in flags:
+ if 'QnanException' in flags:
+ code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n'
+ code += '\tFCSR = genInvalidVector(FCSR);\n'
+ code += '\treturn NoFault;'
+ code += '}\n else '
+ code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n'
+ else:
+ sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
+
+ if 'UnorderedTrue' in flags:
+ code += 'cond = 1;\n'
+ elif 'UnorderedFalse' in flags:
+ code += 'cond = 0;\n'
+ else:
+ sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
+
+ code += '} else {\n'
+ code += cond_code + '}'
+ code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
+
+ iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
}};
def format FloatConvertOp(code, *flags) {{
- iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+ import sys
+
+ #Determine Source Type
+ convert = 'fpConvert('
+ if '.sf' in code:
+ code = 'float ' + code + '\n'
+ convert += 'SINGLE_TO_'
+ elif '.df' in code:
+ code = 'double ' + code + '\n'
+ convert += 'DOUBLE_TO_'
+ elif '.uw' in code:
+ code = 'uint32_t ' + code + '\n'
+ convert += 'WORD_TO_'
+ elif '.ud' in code:
+ code = 'uint64_t ' + code + '\n'
+ convert += 'LONG_TO_'
+ else:
+ sys.exit("Error Determining Source Type for Conversion")
+
+ #Determine Destination Type
+ if 'ToSingle' in flags:
+ code += 'Fd.uw = ' + convert + 'SINGLE, '
+ elif 'ToDouble' in flags:
+ code += 'Fd.ud = ' + convert + 'DOUBLE, '
+ elif 'ToWord' in flags:
+ code += 'Fd.uw = ' + convert + 'WORD, '
+ elif 'ToLong' in flags:
+ code += 'Fd.ud = ' + convert + 'LONG, '
+ else:
+ sys.exit("Error Determining Destination Type for Conversion")
+
+ #Figure out how to round value
+ if 'Ceil' in flags:
+ code += 'ceil(val)); '
+ elif 'Floor' in flags:
+ code += 'floor(val)); '
+ elif 'Round' in flags:
+ code += 'roundFP(val, 0)); '
+ elif 'Trunc' in flags:
+ code += 'truncFP(val));'
+ else:
+ code += 'val); '
+
+ iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code))
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+def format FloatAccOp(code, *flags) {{
+ iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -76,34 +291,51 @@ def format Float64Op(code, *flags) {{
exec_output = BasicExecute.subst(iop)
}};
-def format Float64ConvertOp(code, *flags) {{
- code = 'bool cond;\n' + code
- code += 'FCSR = makeCCVector(FCSR, CC,cond);\n'
- iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
-}};
+def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
+ import sys
-def format FloatPSCompareOp(code, *flags) {{
- code = 'bool cond1;\nbool cond2;\n' + code
- code += 'FCSR = makeCCVector(FCSR, CC+1, cond1);\n'
- code += 'FCSR = makeCCVector(FCSR, CC, cond2);\n'
- iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
-}};
+ code = 'bool cond1, cond2;\n'
+ code += 'bool code_block1, code_block2;\n'
+ code += 'code_block1 = code_block2 = true;\n'
-def format FloatPSCompareWithXcptOp(code, *flags) {{
- code = 'bool cond1;\nbool cond2;\n' + code
- code += 'FCSR = makeCCVector(FCSR, CC+1, cond1);\n'
- code += 'FCSR = makeCCVector(FCSR, CC, cond2);\n'
- iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
+ if 'QnanException' in flags:
+ code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n'
+ code += '\tFCSR = genInvalidVector(FCSR);\n'
+ code += 'code_block1 = false;'
+ code += '}\n'
+ code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n'
+ code += '\tFCSR = genInvalidVector(FCSR);\n'
+ code += 'code_block2 = false;'
+ code += '}\n'
+
+ code += 'if (code_block1) {'
+ code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n'
+ if 'UnorderedTrue' in flags:
+ code += 'cond1 = 1;\n'
+ elif 'UnorderedFalse' in flags:
+ code += 'cond1 = 0;\n'
+ else:
+ sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
+ code += '} else {\n'
+ code += cond_code1
+ code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
+
+ code += 'if (code_block2) {'
+ code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n'
+ if 'UnorderedTrue' in flags:
+ code += 'cond2 = 1;\n'
+ elif 'UnorderedFalse' in flags:
+ code += 'cond2 = 0;\n'
+ else:
+ sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
+ code += '} else {\n'
+ code += cond_code2
+ code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
+
+ iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
}};
+
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index 7d38b9ff5..99aee828f 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -4,8 +4,6 @@
//
// Integer operate instructions
//
-
-//Outputs to decoder.hh
output header {{
#include <iostream>
using namespace std;
@@ -25,6 +23,34 @@ output header {{
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+
+ class HiLoOp: public IntOp
+ {
+ protected:
+
+ /// Constructor
+ HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ IntOp(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ class HiLoMiscOp: public HiLoOp
+ {
+ protected:
+
+ /// Constructor
+ HiLoMiscOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ HiLoOp(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+
class IntImmOp : public MipsStaticInst
{
protected:
@@ -52,6 +78,33 @@ output header {{
}};
+// HiLo<Misc> instruction class execute method template.
+// Mainly to get instruction trace data to print out
+// correctly
+def template HiLoExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(code)s;
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
+ //If there are 2 Destination Registers then
+ //concatenate the values for the traceData
+ if(traceData && _numDestRegs == 2) {
+ uint64_t hilo_final_val = (uint64_t)HI << 32 | LO;
+ traceData->setData(hilo_final_val);
+ }
+ }
+ return fault;
+ }
+}};
+
//Outputs to decoder.cc
output decoder {{
std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
@@ -64,7 +117,7 @@ output decoder {{
// it's generally implicit
if (_numDestRegs > 0) {
printReg(ss, _destRegIdx[0]);
- ss << ",";
+ ss << ", ";
}
// just print the first two source regs... if there's
@@ -75,13 +128,47 @@ output decoder {{
}
if (_numSrcRegs > 1) {
- ss << ",";
+ ss << ", ";
+ printReg(ss, _srcRegIdx[1]);
+ }
+
+ return ss.str();
+ }
+
+ std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ //Destination Registers are implicit for HI/LO ops
+ if (_numSrcRegs > 0) {
+ printReg(ss, _srcRegIdx[0]);
+ }
+
+ if (_numSrcRegs > 1) {
+ ss << ", ";
printReg(ss, _srcRegIdx[1]);
}
return ss.str();
}
+ std::string HiLoMiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
+ printReg(ss, _destRegIdx[0]);
+ } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
+ printReg(ss, _srcRegIdx[0]);
+ }
+
+ return ss.str();
+ }
+
std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
@@ -92,15 +179,15 @@ output decoder {{
printReg(ss, _destRegIdx[0]);
}
- ss << ",";
+ ss << ", ";
if (_numSrcRegs > 0) {
printReg(ss, _srcRegIdx[0]);
- ss << ",";
+ ss << ", ";
}
if( mnemonic == "lui")
- ccprintf(ss, "%08p ", sextImm);
+ ccprintf(ss, "0x%x ", sextImm);
else
ss << (int) sextImm;
@@ -109,23 +196,47 @@ output decoder {{
}};
-//Used by decoder.isa
def format IntOp(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
-
- # Figure out if we are creating a IntImmOp or a IntOp
- # by looking at the instruction name
- iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
- strlen = len(name)
- if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
- iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
-
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = OperateNopCheckDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
+ iop = InstObjParams(name, Name, 'IntOp', CodeBlock(code), opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = OperateNopCheckDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+def format IntImmOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'IntImmOp', CodeBlock(code), opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = OperateNopCheckDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
}};
+def format HiLoOp(code, *opt_flags) {{
+ if '.sd' in code:
+ code = 'int64_t ' + code
+ elif '.ud' in code:
+ code = 'uint64_t ' + code
+
+ code += 'HI = val<63:32>;\n'
+ code += 'LO = val<31:0>;\n'
+
+ iop = InstObjParams(name, Name, 'HiLoOp', CodeBlock(code), opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = OperateNopCheckDecode.subst(iop)
+ exec_output = HiLoExecute.subst(iop)
+}};
+
+def format HiLoMiscOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'HiLoMiscOp', CodeBlock(code), opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = OperateNopCheckDecode.subst(iop)
+ exec_output = HiLoExecute.subst(iop)
+}};
+
+
+
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index d5436b308..0997230a2 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -90,15 +90,6 @@ output decoder {{
}};
-def format LoadAddress(code) {{
- iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
-}};
-
-
def template LoadStoreDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
@@ -426,8 +417,70 @@ def template StoreCompleteAcc {{
}
}};
+
+def template MiscMemAccExecute {{
+ Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ EA = xc->getEA();
+
+ if (fault == NoFault) {
+ %(code)s;
+ }
+
+ return NoFault;
+ }
+}};
+
+def template MiscExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ return NoFault;
+ }
+}};
+
+def template MiscInitiateAcc {{
+ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ panic("Misc instruction does not support split access method!");
+ return NoFault;
+ }
+}};
+
+
+def template MiscCompleteAcc {{
+ Fault %(class_name)s::completeAcc(uint8_t *data,
+ %(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ panic("Misc instruction does not support split access method!");
+
+ return NoFault;
+ }
+}};
+
// load instructions use Rt as dest, so check for
-// Rt == 31 to detect nops
+// Rt == 0 to detect nops
def template LoadNopCheckDecode {{
{
MipsStaticInst *i = new %(class_name)s(machInst);
@@ -446,7 +499,6 @@ def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
exec_template_base = 'Load')
}};
-
def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
@@ -454,26 +506,70 @@ def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
exec_template_base = 'Store')
}};
-//FP loads are offloaded to these formats for now ...
-def format LoadFloatMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
+def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
- decode_template = BasicDecode,
+ decode_template = LoadNopCheckDecode,
exec_template_base = 'Load')
}};
+def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
+ mem_flags = [], inst_flags = []) {{
+ (header_output, decoder_output, decode_block, exec_output) = \
+ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ exec_template_base = 'Store')
+}};
+
+def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
+ mem_flags = [], inst_flags = []) {{
+ decl_code = 'uint32_t mem_word = Mem.uw;\n'
+ decl_code += 'uint32_t unalign_addr = Rs + disp;\n'
+ decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n'
+ decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
+ decl_code += '\tbyte_offset ^= 3;\n'
+ decl_code += '#endif\n'
+
+ memacc_code = decl_code + memacc_code
+
+ (header_output, decoder_output, decode_block, exec_output) = \
+ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ decode_template = LoadNopCheckDecode,
+ exec_template_base = 'Load')
+}};
-def format StoreFloatMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
+def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
mem_flags = [], inst_flags = []) {{
+ decl_code = 'uint32_t mem_word = 0;\n'
+ decl_code += 'uint32_t unaligned_addr = Rs + disp;\n'
+ decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n'
+ decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
+ decl_code += '\tbyte_offset ^= 3;\n'
+ decl_code += '#endif\n'
+ decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
+ memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
+
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ decode_template = LoadNopCheckDecode,
exec_template_base = 'Store')
}};
+def format Prefetch(ea_code = {{ EA = Rs + disp; }},
+ mem_flags = [], pf_flags = [], inst_flags = []) {{
+ pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
+ pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
+ 'IsDataPrefetch', 'MemReadOp']
+
+ (header_output, decoder_output, decode_block, exec_output) = \
+ LoadStoreBase(name, Name, ea_code,
+ 'xc->prefetch(EA, memAccessFlags);',
+ pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
+
+}};
-def format UnalignedStore(memacc_code, postacc_code,
- ea_code = {{ EA = Rb + disp; }},
+def format StoreCond(memacc_code, postacc_code,
+ ea_code = {{ EA = Rs + disp; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
new file mode 100644
index 000000000..2eae8a24b
--- /dev/null
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -0,0 +1,53 @@
+// -*- mode:c++ -*-
+
+////////////////////////////////////////////////////////////////////
+//
+// MT instructions
+//
+
+output header {{
+ /**
+ * Base class for integer operations.
+ */
+ class MT : public MipsStaticInst
+ {
+ protected:
+
+ /// Constructor
+ MT(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+
+output decoder {{
+ //Edit This Template When MT is Implemented
+ std::string MT::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return "Disassembly of MT instruction\n";
+ }
+}};
+
+def template MTExecute {{
+ //Edit This Template When MT is Implemented
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ //Write the resulting state to the execution context
+ %(op_wb)s;
+
+ //Call into the trap handler with the appropriate fault
+ return No_Fault;
+ }
+}};
+
+// Primary format for integer operate instructions:
+def format MipsMT() {{
+ code = 'panic(\"Mips MT Is Currently Unimplemented.\");\n'
+ iop = InstObjParams(name, Name, 'MT', CodeBlock(code))
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa
index 2aa4816e3..a1a80fc56 100644
--- a/src/arch/mips/isa/formats/noop.isa
+++ b/src/arch/mips/isa/formats/noop.isa
@@ -36,11 +36,7 @@ output decoder {{
std::string Nop::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
-#ifdef SS_COMPATIBLE_DISASSEMBLY
- return originalDisassembly;
-#else
- return csprintf("%-10s (%s)", "nop", originalDisassembly);
-#endif
+ return csprintf("%-10s %s", "nop", originalDisassembly);
}
/// Helper function for decoding nops. Substitute Nop object
@@ -89,6 +85,6 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{
}};
def format Nop() {{
- decode_block = 'return new Nop(\"sll r0,r0,0\",machInst);\n'
+ decode_block = 'return new Nop(\"\",machInst);\n'
}};
diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa
index f5e4076f2..dffa31c04 100644
--- a/src/arch/mips/isa/formats/tlbop.isa
+++ b/src/arch/mips/isa/formats/tlbop.isa
@@ -1,3 +1,5 @@
+// -*- mode:c++ -*-
+
////////////////////////////////////////////////////////////////////
//
// TlbOp instructions
@@ -30,13 +32,10 @@ output decoder {{
def template TlbOpExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
- //Call into the trap handler with the appropriate fault
- return No_Fault;
- }
-
//Write the resulting state to the execution context
%(op_wb)s;
+ //Call into the trap handler with the appropriate fault
return No_Fault;
}
}};
diff --git a/src/arch/mips/isa/formats/trap.isa b/src/arch/mips/isa/formats/trap.isa
index 6884d4fa8..f54efdf69 100644
--- a/src/arch/mips/isa/formats/trap.isa
+++ b/src/arch/mips/isa/formats/trap.isa
@@ -1,3 +1,5 @@
+// -*- mode:c++ -*-
+
////////////////////////////////////////////////////////////////////
//
// Trap instructions
@@ -23,27 +25,26 @@ output header {{
output decoder {{
std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
- return "Disassembly of integer instruction\n";
+ return "Disassembly of trap instruction\n";
}
}};
def template TrapExecute {{
+ //Edit This Template When Traps Are Implemented
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
- //Call into the trap handler with the appropriate fault
- return No_Fault;
- }
-
//Write the resulting state to the execution context
%(op_wb)s;
+ //Call into the trap handler with the appropriate fault
return No_Fault;
}
}};
-// Primary format for integer operate instructions:
def format Trap(code, *flags) {{
- code = 'bool cond;\n' + code;
+ code = 'panic(\"'
+ code += 'Trap Exception Handler Is Currently Not Implemented.'
+ code += '\");'
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index 8e42da499..cd079a32a 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -25,13 +25,6 @@
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
-
-////////////////////////////////////////////////////////////////////
-//
-// Unimplemented instructions
-//
output header {{
/**
@@ -103,11 +96,7 @@ output decoder {{
WarnUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
-#ifdef SS_COMPATIBLE_DISASSEMBLY
- return csprintf("%-10s", mnemonic);
-#else
return csprintf("%-10s (unimplemented)", mnemonic);
-#endif
}
}};
@@ -127,7 +116,7 @@ output exec {{
Trace::InstRecord *traceData) const
{
if (!warned) {
- warn("instruction '%s' unimplemented\n", mnemonic);
+ warn("\tinstruction '%s' unimplemented\n", mnemonic);
warned = true;
}
@@ -146,28 +135,3 @@ def format WarnUnimpl() {{
decode_block = BasicDecodeWithMnemonic.subst(iop)
}};
-output header {{
- /**
- * Static instruction class for unknown (illegal) instructions.
- * These cause simulator termination if they are executed in a
- * non-speculative mode. This is a leaf class.
- */
- class Unknown : public MipsStaticInst
- {
- public:
- /// Constructor
- Unknown(MachInst _machInst)
- : MipsStaticInst("unknown", _machInst, No_OpClass)
- {
- // don't call execute() (which panics) if we're on a
- // speculative path
- flags[IsNonSpeculative] = true;
- }
-
- %(BasicExecDeclare)s
-
- std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
-}};
-
diff --git a/src/arch/mips/isa/formats/unknown.isa b/src/arch/mips/isa/formats/unknown.isa
index 7c2275598..b4f834651 100644
--- a/src/arch/mips/isa/formats/unknown.isa
+++ b/src/arch/mips/isa/formats/unknown.isa
@@ -34,28 +34,31 @@
//
output header {{
- std::string inst2string(MachInst machInst);
-}};
-output decoder {{
-
-std::string inst2string(MachInst machInst)
-{
- string str = "";
- uint32_t mask = 0x80000000;
-
- for(int i=0; i < 32; i++) {
- if ((machInst & mask) == 0) {
- str += "0";
- } else {
- str += "1";
+ /**
+ * Static instruction class for unknown (illegal) instructions.
+ * These cause simulator termination if they are executed in a
+ * non-speculative mode. This is a leaf class.
+ */
+ class Unknown : public MipsStaticInst
+ {
+ public:
+ /// Constructor
+ Unknown(MachInst _machInst)
+ : MipsStaticInst("unknown", _machInst, No_OpClass)
+ {
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
}
- mask = mask >> 1;
- }
+ %(BasicExecDeclare)s
- return str;
-}
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+output decoder {{
std::string
Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa
index 615160931..63b5f7e5f 100644
--- a/src/arch/mips/isa/formats/util.isa
+++ b/src/arch/mips/isa/formats/util.isa
@@ -90,7 +90,31 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ completeAccTemplate.subst(completeacc_iop))
}};
+output header {{
+ std::string inst2string(MachInst machInst);
+}};
+
+output decoder {{
+
+std::string inst2string(MachInst machInst)
+{
+ string str = "";
+ uint32_t mask = 0x80000000;
+
+ for(int i=0; i < 32; i++) {
+ if ((machInst & mask) == 0) {
+ str += "0";
+ } else {
+ str += "1";
+ }
+ mask = mask >> 1;
+ }
+
+ return str;
+}
+
+}};
output exec {{
using namespace MipsISA;
@@ -124,6 +148,7 @@ output exec {{
#endif
+
}};
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-26 07:55:40 +0000