5 files changed, 34 insertions, 0 deletions

diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index d8e5eb111..1480a5589 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -172,6 +172,13 @@ output decoder {{
 
 }};
 
+output header {{
+        bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num);
+
+        bool isMMUTLB(%(CPU_exec_context)s *xc);
+
+}};
+
 output exec {{
         bool
         isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index b288b7b20..9dfae3f44 100755
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -135,6 +135,12 @@ def template DspHiLoExecute {{
         }
 }};
 
+output header {{
+    bool isDspEnabled(%(CPU_exec_context)s *xc);
+
+    bool isDspPresent(%(CPU_exec_context)s *xc);
+}};
+
 //Outputs to decoder.cc
 output decoder {{
 }};
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 63823f404..e6f0258a0 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -86,6 +86,11 @@ output decoder {{
         }
 }};
 
+output header {{
+        void fpResetCauseBits(%(CPU_exec_context)s *cpu);
+
+}};
+
 output exec {{
         inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
         {
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index 0ef2ac6ae..64d000005 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -96,6 +96,11 @@ output decoder {{
 
 }};
 
+output header {{
+    uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet);
+
+}};
+
 output exec {{
     /** return data in cases where there the size of data is only
         known in the packet
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 41f94e129..b4d00454e 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -84,6 +84,17 @@ output decoder {{
     }
 }};
 
+output header {{
+   void getThrRegExValues(%(CPU_exec_context)s *xc,
+                          MipsISA::VPEConf0Reg &vpe_conf0,
+                          MipsISA::TCBindReg &tc_bind_mt,
+                          MipsISA::TCBindReg &tc_bind,
+                          MipsISA::VPEControlReg &vpe_control,
+                          MipsISA::MVPConf0Reg &mvp_conf0);
+
+   void getMTExValues(%(CPU_exec_context)s *xc, MipsISA::Config3Reg &config3);
+}};
+
 output exec {{
     void getThrRegExValues(%(CPU_exec_context)s *xc,
             VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt,