diff options
Diffstat (limited to 'src/arch/mips/isa/operands.isa')
| -rw-r--r-- | src/arch/mips/isa/operands.isa | 50 |
1 files changed, 47 insertions, 3 deletions
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa index b89eb5249..609708a13 100644 --- a/src/arch/mips/isa/operands.isa +++ b/src/arch/mips/isa/operands.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2007 MIPS Technologies, Inc. // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -27,6 +27,7 @@ // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Authors: Korey Sewell +// Jaidev Patwardhan def operand_types {{ 'sb' : ('signed int', 8), @@ -39,7 +40,6 @@ def operand_types {{ 'ud' : ('unsigned int', 64), 'sf' : ('float', 32), 'df' : ('float', 64), - 'qf' : ('float', 128) }}; def operands {{ @@ -106,9 +106,17 @@ def operands {{ #Status Control Reg 'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1), + #LL Flag + 'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1), + + # Index Register + 'Index':('ControlReg','uw','MipsISA::Index',None,1), + + #Special cases for when a Control Register Access is dependent on #a combination of bitfield indices (handles MTCO & MFCO) - 'CP0_RD_SEL': ('ControlReg', 'uw', 'RD << 3 | SEL', None, 1), + # Fixed to allow CP0 Register Offset + 'CP0_RD_SEL': ('IControlReg', 'uw', '(RD << 3 | SEL) + Ctrl_Base_DepTag', None, 1), #MT Control Regs 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1), @@ -120,10 +128,28 @@ def operands {{ 'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1), 'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1), + #CP0 Control Regs + 'EntryHi': ('ControlReg','uw', 'MipsISA::EntryHi',None,1), + 'EntryLo0': ('ControlReg','uw', 'MipsISA::EntryLo0',None,1), + 'EntryLo1': ('ControlReg','uw', 'MipsISA::EntryLo1',None,1), + 'PageMask': ('ControlReg','uw', 'MipsISA::PageMask',None,1), + 'Random': ('ControlReg','uw', 'MipsISA::CP0_Random',None,1), + 'ErrorEPC': ('ControlReg','uw', 'MipsISA::ErrorEPC',None,1), + 'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1), + 'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1), + 'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1), + 'Config': ('ControlReg','uw', 'MipsISA::Config',None,1), + 'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1), + 'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1), + 'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1), + 'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1), + + # named bitfields of Control Regs 'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), + 'Status_BEV': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), @@ -132,6 +158,24 @@ def operands {{ 'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3), + 'Config_MT': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 1), + 'Config1_CA': ('ControlBitfield', 'uw', 'MipsISA::Config1', None, 1), + 'Config3_SP': ('ControlBitfield', 'uw', 'MipsISA::Config3', None, 1), + 'PageGrain_ESP': ('ControlBitfield', 'uw', 'MipsISA::PageGrain', None, 1), + 'Cause_EXCCODE': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4), + 'Cause_TI': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4), + 'IntCtl_IPTI': ('ControlBitfield', 'uw', 'MipsISA::IntCtl', None, 4), + 'EntryHi_ASID': ('ControlBitfield', 'uw', 'MipsISA::EntryHi', None, 1), + 'EntryLo0_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), + 'EntryLo0_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 3), + 'EntryLo0_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), + 'EntryLo0_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), + 'EntryLo0_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), + 'EntryLo1_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), + 'EntryLo1_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 3), + 'EntryLo1_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), + 'EntryLo1_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), + 'EntryLo1_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), # named bitfields of Debug Regs 'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1), |