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-rw-r--r--src/arch/mips/isa/operands.isa103
1 files changed, 52 insertions, 51 deletions
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index 1af8857cc..50726cd30 100644
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -56,29 +56,29 @@ def operands {{
'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
#Special Integer Reg operands
- 'LO0': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 6),
- 'HI0': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 7),
+ 'LO0': ('IntReg', 'uw','INTREG_LO', 'IsInteger', 6),
+ 'HI0': ('IntReg', 'uw','INTREG_HI', 'IsInteger', 7),
#Bitfield-dependent HI/LO Register Access
- 'LO_RD_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACDST*3', None, 6),
- 'HI_RD_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACDST*3', None, 7),
- 'LO_RS_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACSRC*3', None, 6),
- 'HI_RS_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACSRC*3', None, 7),
+ 'LO_RD_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACDST*3', None, 6),
+ 'HI_RD_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACDST*3', None, 7),
+ 'LO_RS_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACSRC*3', None, 6),
+ 'HI_RS_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACSRC*3', None, 7),
#DSP Special Purpose Integer Operands
- 'DSPControl': ('IntReg', 'uw', 'MipsISA::DSPControl', None, 8),
- 'DSPLo0': ('IntReg', 'uw', 'MipsISA::LO', None, 1),
- 'DSPHi0': ('IntReg', 'uw', 'MipsISA::HI', None, 1),
- 'DSPACX0': ('IntReg', 'uw', 'MipsISA::DSPACX0', None, 1),
- 'DSPLo1': ('IntReg', 'uw', 'MipsISA::DSPLo1', None, 1),
- 'DSPHi1': ('IntReg', 'uw', 'MipsISA::DSPHi1', None, 1),
- 'DSPACX1': ('IntReg', 'uw', 'MipsISA::DSPACX1', None, 1),
- 'DSPLo2': ('IntReg', 'uw', 'MipsISA::DSPLo2', None, 1),
- 'DSPHi2': ('IntReg', 'uw', 'MipsISA::DSPHi2', None, 1),
- 'DSPACX2': ('IntReg', 'uw', 'MipsISA::DSPACX2', None, 1),
- 'DSPLo3': ('IntReg', 'uw', 'MipsISA::DSPLo3', None, 1),
- 'DSPHi3': ('IntReg', 'uw', 'MipsISA::DSPHi3', None, 1),
- 'DSPACX3': ('IntReg', 'uw', 'MipsISA::DSPACX3', None, 1),
+ 'DSPControl': ('IntReg', 'uw', 'INTREG_DSP_CONTROL', None, 8),
+ 'DSPLo0': ('IntReg', 'uw', 'INTREG_LO', None, 1),
+ 'DSPHi0': ('IntReg', 'uw', 'INTREG_HI', None, 1),
+ 'DSPACX0': ('IntReg', 'uw', 'INTREG_DSP_ACX0', None, 1),
+ 'DSPLo1': ('IntReg', 'uw', 'INTREG_DSP_LO1', None, 1),
+ 'DSPHi1': ('IntReg', 'uw', 'INTREG_DSP_HI1', None, 1),
+ 'DSPACX1': ('IntReg', 'uw', 'INTREG_DSP_ACX1', None, 1),
+ 'DSPLo2': ('IntReg', 'uw', 'INTREG_DSP_LO2', None, 1),
+ 'DSPHi2': ('IntReg', 'uw', 'INTREG_DSP_HI2', None, 1),
+ 'DSPACX2': ('IntReg', 'uw', 'INTREG_DSP_ACX2', None, 1),
+ 'DSPLo3': ('IntReg', 'uw', 'INTREG_DSP_LO3', None, 1),
+ 'DSPHi3': ('IntReg', 'uw', 'INTREG_DSP_HI3', None, 1),
+ 'DSPACX3': ('IntReg', 'uw', 'INTREG_DSP_ACX3', None, 1),
#Floating Point Reg Operands
'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
@@ -87,11 +87,11 @@ def operands {{
'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
#Special Purpose Floating Point Control Reg Operands
- 'FIR': ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1),
- 'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2),
- 'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3),
- 'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3),
- 'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3),
+ 'FIR': ('FloatReg', 'uw', 'FLOATREG_FIR', 'IsFloating', 1),
+ 'FCCR': ('FloatReg', 'uw', 'FLOATREG_FCCR', 'IsFloating', 2),
+ 'FEXR': ('FloatReg', 'uw', 'FLOATREG_FEXR', 'IsFloating', 3),
+ 'FENR': ('FloatReg', 'uw', 'FLOATREG_FENR', 'IsFloating', 3),
+ 'FCSR': ('FloatReg', 'uw', 'FLOATREG_FCSR', 'IsFloating', 3),
#Operands For Paired Singles FP Operations
'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
@@ -104,44 +104,45 @@ def operands {{
'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
#Status Control Reg
- 'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1),
+ 'Status': ('ControlReg', 'uw', 'MISCREG_STATUS', None, 1),
#LL Flag
- 'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1),
+ 'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1),
# Index Register
- 'Index':('ControlReg','uw','MipsISA::Index',None,1),
+ 'Index':('ControlReg','uw','MISCREG_INDEX',None,1),
'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
#MT Control Regs
- 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1),
- 'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1),
- 'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1),
- 'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1),
- 'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1),
- 'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1),
- 'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1),
- 'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1),
+ 'MVPConf0': ('ControlReg', 'uw', 'MISCREG_MVP_CONF0', None, 1),
+ 'MVPControl': ('ControlReg', 'uw', 'MISCREG_MVP_CONTROL', None, 1),
+ 'TCBind': ('ControlReg', 'uw', 'MISCREG_TC_BIND', None, 1),
+ 'TCStatus': ('ControlReg', 'uw', 'MISCREG_TC_STATUS', None, 1),
+ 'TCRestart': ('ControlReg', 'uw', 'MISCREG_TC_RESTART', None, 1),
+ 'VPEConf0': ('ControlReg', 'uw', 'MISCREG_VPE_CONF0', None, 1),
+ 'VPEControl': ('ControlReg', 'uw', 'MISCREG_VPE_CONTROL', None, 1),
+ 'YQMask': ('ControlReg', 'uw', 'MISCREG_YQMASK', None, 1),
#CP0 Control Regs
- 'EntryHi': ('ControlReg','uw', 'MipsISA::EntryHi',None,1),
- 'EntryLo0': ('ControlReg','uw', 'MipsISA::EntryLo0',None,1),
- 'EntryLo1': ('ControlReg','uw', 'MipsISA::EntryLo1',None,1),
- 'PageMask': ('ControlReg','uw', 'MipsISA::PageMask',None,1),
- 'Random': ('ControlReg','uw', 'MipsISA::CP0_Random',None,1),
- 'ErrorEPC': ('ControlReg','uw', 'MipsISA::ErrorEPC',None,1),
- 'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1),
- 'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1),
- 'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1),
- 'Config': ('ControlReg','uw', 'MipsISA::Config',None,1),
- 'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1),
- 'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1),
- 'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1),
- 'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1),
- 'Debug': ('ControlReg','uw', 'MipsISA::Debug',None,1),
- 'Cause': ('ControlReg','uw', 'MipsISA::Cause',None,1),
+ 'EntryHi': ('ControlReg','uw', 'MISCREG_ENTRYHI',None,1),
+ 'EntryLo0': ('ControlReg','uw', 'MISCREG_ENTRYLO0',None,1),
+ 'EntryLo1': ('ControlReg','uw', 'MISCREG_ENTRYLO1',None,1),
+ 'PageMask': ('ControlReg','uw', 'MISCREG_PAGEMASK',None,1),
+ 'Random': ('ControlReg','uw', 'MISCREG_CP0_RANDOM',None,1),
+ 'ErrorEPC': ('ControlReg','uw', 'MISCREG_ERROR_EPC',None,1),
+ 'EPC': ('ControlReg','uw', 'MISCREG_EPC',None,1),
+ 'DEPC': ('ControlReg','uw', 'MISCREG_DEPC',None,1),
+ 'IntCtl': ('ControlReg','uw', 'MISCREG_INTCTL',None,1),
+ 'SRSCtl': ('ControlReg','uw', 'MISCREG_SRSCTL',None,1),
+ 'Config': ('ControlReg','uw', 'MISCREG_CONFIG',None,1),
+ 'Config3': ('ControlReg','uw', 'MISCREG_CONFIG3',None,1),
+ 'Config1': ('ControlReg','uw', 'MISCREG_CONFIG1',None,1),
+ 'Config2': ('ControlReg','uw', 'MISCREG_CONFIG2',None,1),
+ 'PageGrain': ('ControlReg','uw', 'MISCREG_PAGEGRAIN',None,1),
+ 'Debug': ('ControlReg','uw', 'MISCREG_DEBUG',None,1),
+ 'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1),
#Memory Operand
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 03:43:31 +0000