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-rw-r--r--src/arch/mips/isa/base.isa64
-rw-r--r--src/arch/mips/isa/bitfields.isa66
-rw-r--r--src/arch/mips/isa/decoder.isa648
-rw-r--r--src/arch/mips/isa/formats/basic.isa67
-rw-r--r--src/arch/mips/isa/formats/branch.isa67
-rw-r--r--src/arch/mips/isa/formats/control.isa189
-rwxr-xr-xsrc/arch/mips/isa/formats/dsp.isa65
-rw-r--r--src/arch/mips/isa/formats/formats.isa60
-rw-r--r--src/arch/mips/isa/formats/fp.isa66
-rw-r--r--src/arch/mips/isa/formats/int.isa64
-rw-r--r--src/arch/mips/isa/formats/mem.isa229
-rw-r--r--src/arch/mips/isa/formats/mt.isa70
-rw-r--r--src/arch/mips/isa/formats/noop.isa60
-rw-r--r--src/arch/mips/isa/formats/tlbop.isa60
-rw-r--r--src/arch/mips/isa/formats/trap.isa102
-rw-r--r--src/arch/mips/isa/formats/unimp.isa195
-rw-r--r--src/arch/mips/isa/formats/unknown.isa4
-rw-r--r--src/arch/mips/isa/formats/util.isa73
-rw-r--r--src/arch/mips/isa/includes.isa61
-rw-r--r--src/arch/mips/isa/main.isa60
-rw-r--r--src/arch/mips/isa/operands.isa108
21 files changed, 1647 insertions, 731 deletions
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index e8e1c856e..63010eb94 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -1,32 +1,38 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
////////////////////////////////////////////////////////////////////
//
@@ -82,7 +88,7 @@ output decoder {{
// Need to find standard way to not print
// this info. Maybe add bool variable to
// class?
- if (strcmp(mnemonic, "syscall") != 0) {
+ if (mnemonic != "syscall") {
if(_numDestRegs > 0){
printReg(ss, _destRegIdx[0]);
}
@@ -100,7 +106,7 @@ output decoder {{
// Should we define a separate inst. class
// just for two insts?
- if (strcmp(mnemonic, "sll") == 0 || strcmp(mnemonic, "sra") == 0) {
+ if(mnemonic == "sll" || mnemonic == "sra"){
ccprintf(ss,", %d",SA);
}
diff --git a/src/arch/mips/isa/bitfields.isa b/src/arch/mips/isa/bitfields.isa
index 87be5ad13..9352e80bf 100644
--- a/src/arch/mips/isa/bitfields.isa
+++ b/src/arch/mips/isa/bitfields.isa
@@ -1,34 +1,41 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
+// Jaidev Patwardhan
+
-//@TODO: Make sure the naming convention is consistent here.
////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
@@ -119,3 +126,6 @@ def bitfield BP <12:11>;
def bitfield POS <10: 6>;
def bitfield MT_U <5:5>;
def bitfield MT_H <4:4>;
+
+//Cache Ops
+def bitfield CACHE_OP <20:16>;
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 40ea223f6..eb1b0390a 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -1,33 +1,40 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
-// Brett Miller
+// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
+// Brett Miller
+// Jaidev Patwardhan
////////////////////////////////////////////////////////////////////
//
@@ -57,8 +64,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode RS {
0x0: decode RT_RD {
0x0: decode SA default Nop::nop() {
- 0x1: WarnUnimpl::ssnop();
- 0x3: WarnUnimpl::ehb();
+ 0x1: ssnop({{;}});
+ 0x3: ehb({{;}});
}
default: sll({{ Rd = Rt.uw << SA; }});
}
@@ -119,8 +126,8 @@ decode OPCODE_HI default Unknown::unknown() {
//used to distinguish JR from JR.HB and JALR from JALR.HB"
format Jump {
0x0: decode HINT {
- 0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
- default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
+ 0x1: jr_hb({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");}; }}, IsReturn, ClearHazards);
+ default: jr({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");};}}, IsReturn);
}
0x1: decode HINT {
@@ -133,28 +140,31 @@ decode OPCODE_HI default Unknown::unknown() {
format BasicOp {
0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
+#if FULL_SYSTEM
+ 0x4: syscall({{
+ fault = new SystemCallFault();
+ }});
+#else
0x4: syscall({{ xc->syscall(R2); }},
- IsSerializeAfter, IsNonSpeculative,
- IsSyscall);
+ IsSerializing, IsNonSpeculative);
+#endif
0x7: sync({{ ; }}, IsMemBarrier);
+ 0x5: break({{fault = new BreakpointFault();}});
}
- format FailUnimpl {
- 0x5: break();
- }
}
0x2: decode FUNCTION_LO {
- 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }});
+ 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, IntMultOp, IsIprAccess);
0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
- 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }});
+ 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, IntMultOp, IsIprAccess);
0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
}
0x3: decode FUNCTION_LO {
format HiLoRdSelValOp {
- 0x0: mult({{ val = Rs.sd * Rt.sd; }});
- 0x1: multu({{ val = Rs.ud * Rt.ud; }});
+ 0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp);
+ 0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp);
}
format HiLoOp {
@@ -162,21 +172,55 @@ decode OPCODE_HI default Unknown::unknown() {
HI0 = Rs.sd % Rt.sd;
LO0 = Rs.sd / Rt.sd;
}
- }});
+ }}, IntDivOp);
+
0x3: divu({{ if (Rt.ud != 0) {
HI0 = Rs.ud % Rt.ud;
LO0 = Rs.ud / Rt.ud;
}
- }});
+ }}, IntDivOp);
}
}
0x4: decode HINT {
0x0: decode FUNCTION_LO {
format IntOp {
- 0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
+ 0x0: add({{ /* More complicated since an ADD can cause an arithmetic overflow exception */
+ int64_t Src1 = Rs.sw;
+ int64_t Src2 = Rt.sw;
+ int64_t temp_result;
+#if FULL_SYSTEM
+ if(((Src1 >> 31) & 1) == 1)
+ Src1 |= 0x100000000LL;
+#endif
+ temp_result = Src1 + Src2;
+#if FULL_SYSTEM
+ if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){
+#endif
+ Rd.sw = temp_result;
+#if FULL_SYSTEM
+ } else{
+ fault = new ArithmeticFault();
+ }
+#endif
+
+ }});
0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
- 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
+ 0x2: sub({{
+ /* More complicated since an SUB can cause an arithmetic overflow exception */
+ int64_t Src1 = Rs.sw;
+ int64_t Src2 = Rt.sw;
+ int64_t temp_result = Src1 - Src2;
+#if FULL_SYSTEM
+ if(((temp_result >> 31) & 1) == ((temp_result>>32) & 1)){
+#endif
+ Rd.sw = temp_result;
+#if FULL_SYSTEM
+ } else{
+ fault = new ArithmeticFault();
+ }
+#endif
+ }});
0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
0x4: and({{ Rd = Rs & Rt;}});
0x5: or({{ Rd = Rs | Rt;}});
@@ -200,7 +244,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
- 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
+ 0x3: tltu({{ cond = (Rs.uw < Rt.uw); }});
0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
}
@@ -218,13 +262,13 @@ decode OPCODE_HI default Unknown::unknown() {
}
0x1: decode REGIMM_LO {
- format Trap {
- 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
- 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
- 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
- 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
- 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
- 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
+ format TrapImm {
+ 0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }});
+ 0x1: tgeiu({{ cond = (Rs.uw >= (uint32_t)((int32_t)((int16_t)INTIMM))); }});
+ 0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }});
+ 0x3: tltiu({{ cond = (Rs.uw < (uint32_t)((int32_t)((int16_t)INTIMM))); }});
+ 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM);}});
+ 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM);}});
}
}
@@ -268,7 +312,25 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: decode OPCODE_LO {
format IntImmOp {
- 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
+ 0x0: addi({{
+ int64_t Src1 = Rs.sw;
+ int64_t Src2 = imm;
+ int64_t temp_result;
+#if FULL_SYSTEM
+ if(((Src1 >> 31) & 1) == 1)
+ Src1 |= 0x100000000LL;
+#endif
+ temp_result = Src1 + Src2;
+#if FULL_SYSTEM
+ if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){
+#endif
+ Rt.sw = temp_result;
+#if FULL_SYSTEM
+ } else{
+ fault = new ArithmeticFault();
+ }
+#endif
+ }});
0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
@@ -294,12 +356,32 @@ decode OPCODE_HI default Unknown::unknown() {
//Table A-11 MIPS32 COP0 Encoding of rs Field
0x0: decode RS_MSB {
0x0: decode RS {
- format CP0Control {
- 0x0: mfc0({{ Rt = CP0_RD_SEL; }});
- 0x4: mtc0({{ CP0_RD_SEL = Rt; }});
- }
-
-
+ format CP0Control {
+ 0x0: mfc0({{ Rt = CP0_RD_SEL;
+ /* Hack for PageMask */
+ if(RD == 5) // PageMask
+ if(Config3_SP == 0 || PageGrain_ESP == 0)
+ Rt &= 0xFFFFE7FF;
+ }});
+ 0x4: mtc0({{ CP0_RD_SEL = Rt;
+
+ if(RD == 11) // Compare{
+ if(Cause_TI == 1){
+ Cause_TI = 0;
+ MiscReg cause = xc->readMiscRegNoEffect(MipsISA::Cause);
+ int Offset = 10; // corresponding to Cause_IP0
+ Offset += ((IntCtl_IPTI) - 2);
+ replaceBits(cause,Offset,Offset,0);
+ xc->setMiscRegNoEffect(MipsISA::Cause,cause);
+ }
+
+ }});
+ }
+ format CP0Unimpl {
+ 0x1: dmfc0();
+ 0x5: dmtc0();
+ default: unknown();
+ }
format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions
0x8: decode MT_U {
0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) +
@@ -321,6 +403,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }});
0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }});
0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }});
+ default: CP0Unimpl::unknown();
}
0x2: decode MT_H {
0x0: mftc1({{ data = xc->readRegOtherThread(RT +
@@ -329,7 +412,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
FP_Base_DepTag);
}});
- }
+ }
0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR +
FP_Base_DepTag);
switch (RT)
@@ -357,8 +440,9 @@ decode OPCODE_HI default Unknown::unknown() {
fatal("FP Control Value (%d) Not Valid");
}
}});
+ default: CP0Unimpl::unknown();
}
- }
+ }
}
format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions
@@ -404,6 +488,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt);
}});
0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }});
+ default: CP0Unimpl::unknown();
+
}
0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD +
FP_Base_DepTag);
@@ -446,6 +532,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
xc->setRegOtherThread(FCSR, data);
}});
+ default: CP0Unimpl::unknown();
}
}
}
@@ -466,9 +553,12 @@ decode OPCODE_HI default Unknown::unknown() {
MVPControl = insertBits(MVPControl, MVPC_EVP, 1);
}
}});
+ default:CP0Unimpl::unknown();
}
+ default:CP0Unimpl::unknown();
}
- }
+ default:CP0Unimpl::unknown();
+ }
0x1: decode POS {
0xF: decode SEL {
@@ -479,9 +569,11 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: emt({{ Rt = VPEControl;
VPEControl = insertBits(VPEControl, VPEC_TE, 1);
}});
-
+ default:CP0Unimpl::unknown();
}
+ default:CP0Unimpl::unknown();
}
+ default:CP0Unimpl::unknown();
}
}
0xC: decode POS {
@@ -508,15 +600,16 @@ decode OPCODE_HI default Unknown::unknown() {
fault = new ReservedInstructionFault();
}
}});
+ default:CP0Unimpl::unknown();
}
}
+ default: CP0Unimpl::unknown();
}
-
format CP0Control {
0xA: rdpgpr({{
if(Config_AR >= 1)
{ // Rev 2 of the architecture
- Rd = xc->tcBase()->readIntReg(Rt + NumIntRegs * SRSCtl_PSS);
+ Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS);
}
else
{
@@ -526,7 +619,8 @@ decode OPCODE_HI default Unknown::unknown() {
0xE: wrpgpr({{
if(Config_AR >= 1)
{ // Rev 2 of the architecture
- xc->tcBase()->setIntReg(Rd + NumIntRegs * SRSCtl_PSS,Rt);
+ xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt);
+ // warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl);
}
else
{
@@ -534,48 +628,210 @@ decode OPCODE_HI default Unknown::unknown() {
}
}});
-
}
- }
+ }
//Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
0x1: decode FUNCTION {
format CP0Control {
0x18: eret({{
+ DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
+ // Ugly hack to get the value of Status_EXL
+ if(Status_EXL == 1){
+ DPRINTF(MipsPRA,"ERET EXL Hack\n");
+ }
if(Status_ERL == 1){
Status_ERL = 0;
NPC = ErrorEPC;
+ NNPC = ErrorEPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
}
- else{
+ else {
NPC = EPC;
+ NNPC = EPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
Status_EXL = 0;
- if(Config_AR >= 1 && SRSCtl_HSS > 0 && Status_BEV == 0){
+ if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){
SRSCtl_CSS = SRSCtl_PSS;
+ xc->setShadowSet(SRSCtl_PSS);
}
}
- // LLFlag = 0;
- // ClearHazards(); ?
- }});
+ LLFlag = 0;
+ }},IsReturn,IsSerializing,IsERET);
0x1F: deret({{
- //if(Debug_DM == 1){
- //Debug_DM = 1;
- //Debug_IEXI = 0;
- //NPC = DEPC;
- //}
- panic("deret not implemented");
- }});
+ // if(EJTagImplemented()) {
+ if(Debug_DM == 1){
+ Debug_DM = 1;
+ Debug_IEXI = 0;
+ NPC = DEPC;
+ }
+ else
+ {
+ // Undefined;
+ }
+ //} // EJTag Implemented
+ //else {
+ // Reserved Instruction Exception
+ //}
+ }},IsReturn,IsSerializing,IsERET);
}
+ format CP0TLB {
+ 0x01: tlbr({{
+ MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF);
+ if(PTEntry == NULL)
+ {
+ fatal("Invalid PTE Entry received on a TLBR instruction\n");
+ }
+ /* Setup PageMask */
+ PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11
+ /* Setup EntryHi */
+ EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid));
+ /* Setup Entry Lo0 */
+ EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G);
+ /* Setup Entry Lo1 */
+ EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G);
+ }}); // Need to hook up to TLB
+
+ 0x02: tlbwi({{
+ //Create PTE
+ MipsISA::PTE NewEntry;
+ //Write PTE
+ NewEntry.Mask = (Addr)(PageMask >> 11);
+ NewEntry.VPN = (Addr)(EntryHi >> 11);
+ /* PageGrain _ ESP Config3 _ SP */
+ if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
+ NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
+ NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
+ }
+ NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
+
+ NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
+ NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
+ NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
+ NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
+ NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
+ NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
+ NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
+ NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
+ NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
+ /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
+ /* Addr Shift Amount for 1KB or larger pages */
+ // warn("PTE->Mask: %x\n",pte->Mask);
+ if((NewEntry.Mask & 0xFFFF) == 3){
+ NewEntry.AddrShiftAmount = 12;
+ } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
+ NewEntry.AddrShiftAmount = 10;
+ } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
+ NewEntry.AddrShiftAmount = 14;
+ } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
+ NewEntry.AddrShiftAmount = 16;
+ } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
+ NewEntry.AddrShiftAmount = 18;
+ } else if((NewEntry.Mask & 0xFF00) == 0x0300){
+ NewEntry.AddrShiftAmount = 20;
+ } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
+ NewEntry.AddrShiftAmount = 22;
+ } else if((NewEntry.Mask & 0xF000) == 0x3000){
+ NewEntry.AddrShiftAmount = 24;
+ } else if((NewEntry.Mask & 0xC000) == 0xC000){
+ NewEntry.AddrShiftAmount = 26;
+ } else if((NewEntry.Mask & 0x30000) == 0x30000){
+ NewEntry.AddrShiftAmount = 28;
+ } else {
+ fatal("Invalid Mask Pattern Detected!\n");
+ }
+ NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
+
+ MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
+ MiscReg c3=xc->readMiscReg(MipsISA::Config3);
+ MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
+ int SP=0;
+ if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
+ SP=1;
+ }
+ Ptr->insertAt(NewEntry,Index & 0x7FFFFFFF,SP);
+ }});
+ 0x06: tlbwr({{
+ //Create PTE
+ MipsISA::PTE NewEntry;
+ //Write PTE
+ NewEntry.Mask = (Addr)(PageMask >> 11);
+ NewEntry.VPN = (Addr)(EntryHi >> 11);
+ /* PageGrain _ ESP Config3 _ SP */
+ if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
+ NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
+ NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
+ }
+ NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
+
+ NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
+ NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
+ NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
+ NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
+ NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
+ NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
+ NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
+ NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
+ NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
+ /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
+ /* Addr Shift Amount for 1KB or larger pages */
+ // warn("PTE->Mask: %x\n",pte->Mask);
+ if((NewEntry.Mask & 0xFFFF) == 3){
+ NewEntry.AddrShiftAmount = 12;
+ } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
+ NewEntry.AddrShiftAmount = 10;
+ } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
+ NewEntry.AddrShiftAmount = 14;
+ } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
+ NewEntry.AddrShiftAmount = 16;
+ } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
+ NewEntry.AddrShiftAmount = 18;
+ } else if((NewEntry.Mask & 0xFF00) == 0x0300){
+ NewEntry.AddrShiftAmount = 20;
+ } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
+ NewEntry.AddrShiftAmount = 22;
+ } else if((NewEntry.Mask & 0xF000) == 0x3000){
+ NewEntry.AddrShiftAmount = 24;
+ } else if((NewEntry.Mask & 0xC000) == 0xC000){
+ NewEntry.AddrShiftAmount = 26;
+ } else if((NewEntry.Mask & 0x30000) == 0x30000){
+ NewEntry.AddrShiftAmount = 28;
+ } else {
+ fatal("Invalid Mask Pattern Detected!\n");
+ }
+ NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
+
+ MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
+ MiscReg c3=xc->readMiscReg(MipsISA::Config3);
+ MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
+ int SP=0;
+ if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
+ SP=1;
+ }
+ Ptr->insertAt(NewEntry,Random,SP);
+ }});
- format FailUnimpl {
- 0x01: tlbr(); // Need to hook up to TLB
- 0x02: tlbwi(); // Need to hook up to TLB
- 0x06: tlbwr();// Need to hook up to TLB
- 0x08: tlbp();// Need to hook up to TLB
-
- 0x20: wait();
- }
+ 0x08: tlbp({{
+ int TLB_Index;
+ Addr VPN;
+ if(PageGrain_ESP == 1 && Config3_SP ==1){
+ VPN = EntryHi >> 11;
+ } else {
+ VPN = ((EntryHi >> 11) & 0xFFFFFFFC); // Mask off lower 2 bits
+ }
+ TLB_Index = xc->tcBase()->getITBPtr()->probeEntry(VPN,EntryHi_ASID);
+ if(TLB_Index != -1){ // Check TLB for entry matching EntryHi
+ Index=TLB_Index;
+ // warn("\ntlbp: Match Found!\n");
+ } else {// else, set Index = 1<<31
+ Index = (1<<31);
+ }
+ }});
+ }
+ format CP0Unimpl {
+ 0x20: wait();
+ }
+ default: CP0Unimpl::unknown();
}
}
@@ -607,8 +863,9 @@ decode OPCODE_HI default Unknown::unknown() {
Rt = FCSR;
break;
default:
- panic("FP Control Value (%d) Not Valid");
+ warn("FP Control Value (%d) Not Valid");
}
+ // warn("FCSR: %x, FS: %d, FIR: %x, Rt: %x\n",FCSR, FS, FIR, Rt);
}});
0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
@@ -658,24 +915,37 @@ decode OPCODE_HI default Unknown::unknown() {
}});
}
- }
-
- 0x1: decode ND {
- format Branch {
- 0x0: decode TF {
- 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
- }});
- 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
- }});
- }
- 0x1: decode TF {
- 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
- }}, Likely);
- 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
- }}, Likely);
- }
+ format CP1Unimpl {
+ 0x1: dmfc1();
+ 0x5: dmtc1();
}
- }
+ }
+
+ 0x1:
+ decode RS_LO {
+ 0x0:
+ decode ND {
+ format Branch {
+ 0x0: decode TF {
+ 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
+ }});
+ 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
+ }});
+ }
+ 0x1: decode TF {
+ 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
+ }}, Likely);
+ 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
+ }}, Likely);
+ }
+ }
+ }
+ format CP1Unimpl {
+ 0x1: bc1any2();
+ 0x2: bc1any4();
+ default: unknown();
+ }
+ }
}
0x1: decode RS_HI {
@@ -735,7 +1005,11 @@ decode OPCODE_HI default Unknown::unknown() {
0x5: recip_s({{ Fd = 1 / Fs; }});
0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
}
+ format CP1Unimpl {
+ default: unknown();
+ }
}
+ 0x3: CP1Unimpl::unknown();
0x4: decode FUNCTION_LO {
format FloatConvertOp {
@@ -748,7 +1022,11 @@ decode OPCODE_HI default Unknown::unknown() {
Fd.ud = (uint64_t) Fs.uw << 32 |
(uint64_t) Ft.uw;
}});
+ format CP1Unimpl {
+ default: unknown();
+ }
}
+ 0x5: CP1Unimpl::unknown();
0x6: decode FUNCTION_LO {
format FloatCompareOp {
@@ -851,14 +1129,18 @@ decode OPCODE_HI default Unknown::unknown() {
0x5: recip_d({{ Fd.df = 1 / Fs.df }});
0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }});
}
- }
+ format CP1Unimpl {
+ default: unknown();
+ }
+ }
0x4: decode FUNCTION_LO {
format FloatConvertOp {
0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle);
0x4: cvt_w_d({{ val = Fs.df; }}, ToWord);
0x5: cvt_l_d({{ val = Fs.df; }}, ToLong);
}
+ default: CP1Unimpl::unknown();
}
0x6: decode FUNCTION_LO {
@@ -902,15 +1184,20 @@ decode OPCODE_HI default Unknown::unknown() {
UnorderedTrue, QnanException);
}
}
+ default: CP1Unimpl::unknown();
}
+ 0x2: CP1Unimpl::unknown();
+ 0x3: CP1Unimpl::unknown();
+ 0x7: CP1Unimpl::unknown();
//Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
0x4: decode FUNCTION {
format FloatConvertOp {
0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle);
0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble);
- 0x26: FailUnimpl::cvt_ps_w();
+ 0x26: CP1Unimpl::cvt_ps_w();
}
+ default: CP1Unimpl::unknown();
}
//Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
@@ -920,8 +1207,9 @@ decode OPCODE_HI default Unknown::unknown() {
format FloatConvertOp {
0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle);
0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble);
- 0x26: FailUnimpl::cvt_ps_l();
+ 0x26: CP1Unimpl::cvt_ps_l();
}
+ default: CP1Unimpl::unknown();
}
//Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
@@ -954,9 +1242,10 @@ decode OPCODE_HI default Unknown::unknown() {
Fd1.sf = -(Fs1.sf);
Fd2.sf = -(Fs2.sf);
}});
+ default: CP1Unimpl::unknown();
}
}
-
+ 0x1: CP1Unimpl::unknown();
0x2: decode FUNCTION_LO {
0x1: decode MOVCF {
format Float64Op {
@@ -989,11 +1278,13 @@ decode OPCODE_HI default Unknown::unknown() {
Fs2 : Fd2;
}});
}
+ default: CP1Unimpl::unknown();
}
-
+ 0x3: CP1Unimpl::unknown();
0x4: decode FUNCTION_LO {
0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }});
+ default: CP1Unimpl::unknown();
}
0x5: decode FUNCTION_LO {
@@ -1013,6 +1304,7 @@ decode OPCODE_HI default Unknown::unknown() {
Ft2.uw;
}});
}
+ default: CP1Unimpl::unknown();
}
0x6: decode FUNCTION_LO {
@@ -1071,12 +1363,13 @@ decode OPCODE_HI default Unknown::unknown() {
}
}
}
+ default: CP1Unimpl::unknown();
}
}
//Table A-19 MIPS32 COP2 Encoding of rs Field
0x2: decode RS_MSB {
- format FailUnimpl {
+ format CP2Unimpl {
0x0: decode RS_HI {
0x0: decode RS_LO {
0x0: mfc2();
@@ -1085,20 +1378,28 @@ decode OPCODE_HI default Unknown::unknown() {
0x4: mtc2();
0x6: ctc2();
0x7: mftc2();
+ default: unknown();
}
0x1: decode ND {
0x0: decode TF {
0x0: bc2f();
0x1: bc2t();
+ default: unknown();
}
0x1: decode TF {
0x0: bc2fl();
0x1: bc2tl();
+ default: unknown();
}
- }
- }
+ default: unknown();
+
+ }
+ default: unknown();
+
+ }
+ default: unknown();
}
}
@@ -1197,13 +1498,13 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode FUNCTION_LO {
0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
Rd.sw = temp1<31:0>;
- }});
+ }}, IntMultOp);
format HiLoRdSelValOp {
- 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }});
- 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }});
- 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }});
- 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }});
+ 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }}, IntMultOp);
+ 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }}, IntMultOp);
+ 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }}, IntMultOp);
+ 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }}, IntMultOp);
}
}
@@ -1286,9 +1587,9 @@ decode OPCODE_HI default Unknown::unknown() {
0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
SATURATE, UNSIGNED, &dspctl ); }});
0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
- MODE_L, &dspctl ); }});
+ MODE_L, &dspctl ); }}, IntMultOp);
0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
- MODE_R, &dspctl ); }});
+ MODE_R, &dspctl ); }}, IntMultOp);
}
}
0x1: decode OP_LO {
@@ -1335,13 +1636,13 @@ decode OPCODE_HI default Unknown::unknown() {
0x3: decode OP_LO {
format DspIntOp {
0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
- MODE_L, &dspctl ); }});
+ MODE_L, &dspctl ); }}, IntMultOp);
0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
- MODE_R, &dspctl ); }});
+ MODE_R, &dspctl ); }}, IntMultOp);
0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
- SATURATE, NOROUND, &dspctl ); }});
+ SATURATE, NOROUND, &dspctl ); }}, IntMultOp);
0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
- SATURATE, ROUND, &dspctl ); }});
+ SATURATE, ROUND, &dspctl ); }}, IntMultOp);
}
}
}
@@ -1559,9 +1860,10 @@ decode OPCODE_HI default Unknown::unknown() {
0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
ROUND, SIGNED ); }});
0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
- NOSATURATE, &dspctl ); }});
+ NOSATURATE, &dspctl ); }}, IntMultOp);
0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
- SATURATE, &dspctl ); }});
+ SATURATE, &dspctl ); }}, IntMultOp);
+
}
}
0x2: decode OP_LO {
@@ -1575,9 +1877,9 @@ decode OPCODE_HI default Unknown::unknown() {
0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
ROUND, SIGNED ); }});
0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
- SATURATE, NOROUND, &dspctl ); }});
+ SATURATE, NOROUND, &dspctl ); }}, IntMultOp);
0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
- SATURATE, ROUND, &dspctl ); }});
+ SATURATE, ROUND, &dspctl ); }}, IntMultOp);
}
}
}
@@ -1603,61 +1905,61 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode OP_LO {
format DspHiLoOp {
0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
- SIMD_FMT_PH, SIGNED, MODE_L ); }});
+ SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp);
0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
- SIMD_FMT_PH, SIGNED, MODE_L ); }});
+ SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp);
0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw,
- ACDST, SIMD_FMT_PH ); }});
+ ACDST, SIMD_FMT_PH ); }}, IntMultOp);
0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
- SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
+ SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp);
0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
- SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
+ SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp);
0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
- SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
+ SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp);
0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw,
- ACDST, SIMD_FMT_PH, &dspctl ); }});
+ ACDST, SIMD_FMT_PH, &dspctl ); }}, IntMultOp);
0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
- SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
+ SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp);
}
}
0x1: decode OP_LO {
format DspHiLoOp {
0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
- SIMD_FMT_PH, SIGNED, MODE_X ); }});
+ SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp);
0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
- SIMD_FMT_PH, SIGNED, MODE_X ); }});
+ SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp);
0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
- SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
+ SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp);
0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
- SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
+ SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp);
0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
- SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
+ SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp);
0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
- SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
+ SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp);
}
}
0x2: decode OP_LO {
format DspHiLoOp {
0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
- MODE_L, SATURATE, &dspctl ); }});
+ MODE_L, SATURATE, &dspctl ); }}, IntMultOp);
0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
- MODE_R, SATURATE, &dspctl ); }});
+ MODE_R, SATURATE, &dspctl ); }}, IntMultOp);
0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
- MODE_L, NOSATURATE, &dspctl ); }});
+ MODE_L, NOSATURATE, &dspctl ); }}, IntMultOp);
0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
- MODE_R, NOSATURATE, &dspctl ); }});
+ MODE_R, NOSATURATE, &dspctl ); }}, IntMultOp);
}
}
0x3: decode OP_LO {
format DspHiLoOp {
0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
- SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
+ SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp);
0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
- SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
+ SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp);
0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
- SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
+ SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp);
0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
- SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
+ SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp);
}
}
}
@@ -1677,9 +1979,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
}
- 0x7: FailUnimpl::rdhwr();
}
-
0x7: decode FUNCTION_LO {
//Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL)
@@ -1735,35 +2035,40 @@ decode OPCODE_HI default Unknown::unknown() {
}
}
}
+ 0x3: decode OP_HI {
+ 0x2: decode OP_LO {
+ 0x3: FailUnimpl::rdhwr();
+ }
+ }
}
}
}
0x4: decode OPCODE_LO {
format LoadMemory {
- 0x0: lb({{ Rt.sw = Mem.sb; }});
- 0x1: lh({{ Rt.sw = Mem.sh; }});
+ 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT);
+ 0x1: lh({{ Rt.sw = Mem.sh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
0x3: lw({{ Rt.sw = Mem.sw; }});
- 0x4: lbu({{ Rt.uw = Mem.ub; }});
- 0x5: lhu({{ Rt.uw = Mem.uh; }});
+ 0x4: lbu({{ Rt.uw = Mem.ub;}}, mem_flags = NO_ALIGN_FAULT);
+ 0x5: lhu({{ Rt.uw = Mem.uh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
}
format LoadUnalignedMemory {
0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
Rt.uw = mem_word << mem_shift |
- Rt.uw & mask(mem_shift);
+ Rt.uw & mask(mem_shift);
}});
0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
- mem_word >> mem_shift;
+ mem_word >> mem_shift;
}});
}
}
0x5: decode OPCODE_LO {
format StoreMemory {
- 0x0: sb({{ Mem.ub = Rt<7:0>; }});
- 0x1: sh({{ Mem.uh = Rt<15:0>; }});
+ 0x0: sb({{ Mem.ub = Rt<7:0>; }}, mem_flags = NO_ALIGN_FAULT);
+ 0x1: sh({{ Mem.uh = Rt<15:0>; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
0x3: sw({{ Mem.uw = Rt<31:0>; }});
}
@@ -1778,8 +2083,12 @@ decode OPCODE_HI default Unknown::unknown() {
mem_word & (mask(reg_shift));
}});
}
-
- 0x7: FailUnimpl::cache();
+ format CP0Control {
+ 0x7: cache({{
+ Addr CacheEA = Rs.uw + OFFSET;
+ fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA);
+ }});
+ }
}
0x6: decode OPCODE_LO {
@@ -1788,7 +2097,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: lwc1({{ Ft.uw = Mem.uw; }});
0x5: ldc1({{ Ft.ud = Mem.ud; }});
}
-
+ 0x2: CP2Unimpl::lwc2();
+ 0x6: CP2Unimpl::ldc2();
0x3: Prefetch::pref();
}
@@ -1800,9 +2110,13 @@ decode OPCODE_HI default Unknown::unknown() {
}}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
format StoreMemory {
- 0x1: swc1({{ Mem.uw = Ft.uw; }});
- 0x5: sdc1({{ Mem.ud = Ft.ud; }});
+ 0x1: swc1({{ Mem.uw = Ft.uw;}});
+ 0x5: sdc1({{ Mem.ud = Ft.ud;}});
}
+
+ 0x2: CP2Unimpl::swc2();
+ 0x6: CP2Unimpl::sdc2();
+
}
}
diff --git a/src/arch/mips/isa/formats/basic.isa b/src/arch/mips/isa/formats/basic.isa
index ec065b865..cba54bb78 100644
--- a/src/arch/mips/isa/formats/basic.isa
+++ b/src/arch/mips/isa/formats/basic.isa
@@ -1,33 +1,39 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Steve Reinhardt
-// Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Steven K. Reinhardt
+// Korey L. Sewell
// Declarations for execute() methods.
def template BasicExecDeclare {{
@@ -66,11 +72,12 @@ def template BasicExecute {{
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
- %(code)s;
-
if(fault == NoFault)
{
+ %(code)s;
+ if(fault == NoFault){
%(op_wb)s;
+ }
}
return fault;
}
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index e786b3d9f..c5f638ccb 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -1,32 +1,38 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
////////////////////////////////////////////////////////////////////
//
@@ -133,9 +139,8 @@ output decoder {{
Addr
Jump::branchTarget(ThreadContext *tc) const
{
- Addr NPC = tc->readPC() + 4;
- uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
- return (Rb & ~3) | (NPC & 1);
+ Addr NPC = tc->readNextPC();
+ return (NPC & 0xF0000000) | (disp);
}
const std::string &
@@ -196,7 +201,7 @@ output decoder {{
ccprintf(ss, "%-10s ", mnemonic);
- if (strcmp(mnemonic, "jal") == 0) {
+ if ( mnemonic == "jal" ) {
Addr npc = pc + 4;
ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
} else if (_numSrcRegs == 0) {
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 1de2948be..4593aa52b 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -1,32 +1,39 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
+// Jaidev Patwardhan
////////////////////////////////////////////////////////////////////
//
@@ -48,6 +55,19 @@ output header {{
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+ class CP0TLB : public MipsStaticInst
+ {
+ protected:
+
+ /// Constructor
+ CP0TLB(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ MipsStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
class CP1Control : public MipsStaticInst
{
@@ -65,7 +85,7 @@ output header {{
}};
// Basic instruction class execute method template.
-def template ControlExecute {{
+def template CP0Execute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -75,7 +95,7 @@ def template ControlExecute {{
if (isCoprocessorEnabled(xc, 0)) {
%(code)s;
} else {
- fault = new CoprocessorUnusableFault();
+ fault = new CoprocessorUnusableFault(0);
}
if(fault == NoFault)
@@ -86,6 +106,57 @@ def template ControlExecute {{
}
}};
+def template CP1Execute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+ %(op_decl)s;
+ %(op_rd)s;
+
+ if (isCoprocessorEnabled(xc, 1)) {
+ %(code)s;
+ } else {
+ fault = new CoprocessorUnusableFault(1);
+ }
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
+ }
+ return fault;
+ }
+}};
+// Basic instruction class execute method template.
+def template ControlTLBExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+ %(op_decl)s;
+ %(op_rd)s;
+
+#if FULL_SYSTEM
+ if (isCoprocessor0Enabled(xc)) {
+ if(isMMUTLB(xc)){
+ %(code)s;
+ } else {
+ fault = new ReservedInstructionFault();
+ }
+ } else {
+ fault = new CoprocessorUnusableFault(0);
+ }
+#else // Syscall Emulation Mode - No TLB Instructions
+ fault = new ReservedInstructionFault();
+#endif
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
+ }
+ return fault;
+
+ }
+}};
+
//Outputs to decoder.cc
output decoder {{
std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
@@ -94,7 +165,12 @@ output decoder {{
ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
return ss.str();
}
-
+ std::string CP0TLB::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+ ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
+ return ss.str();
+ }
std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
@@ -107,29 +183,65 @@ output decoder {{
output exec {{
bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
{
+ MiscReg Stat = xc->readMiscReg(MipsISA::Status);
switch(cop_num)
{
case 0:
+ {
#if FULL_SYSTEM
- if((xc->readMiscReg(MipsISA::Status) & 0x10000006) == 0 && (xc->readMiscReg(MipsISA::Debug) & 0x40000000 ) == 0) {
- // Unable to use Status_CU0, etc directly, using bitfields & masks
+ MiscReg Dbg = xc->readMiscReg(MipsISA::Debug);
+ if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
+ && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
+ && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
+ // Unable to use Status_CU0, etc directly, using bitfields & masks
return false;
}
#else
//printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
#endif
+ }
break;
case 1:
+ if((Stat & 0x20000000) == 0) // CU1 is reset
+ return false;
break;
case 2:
+ if((Stat & 0x40000000) == 0) // CU2 is reset
+ return false;
break;
case 3:
+ if((Stat & 0x80000000) == 0) // CU3 is reset
+ return false;
break;
default: panic("Invalid Coprocessor Number Specified");
break;
}
return true;
}
+ bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
+ {
+#if FULL_SYSTEM
+ MiscReg Stat = xc->readMiscRegNoEffect(MipsISA::Status);
+ MiscReg Dbg = xc->readMiscRegNoEffect(MipsISA::Debug);
+ if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
+ && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
+ && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
+ // Unable to use Status_CU0, etc directly, using bitfields & masks
+ return false;
+ }
+#else
+ //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
+#endif
+ return true;
+ }
+ bool isMMUTLB(%(CPU_exec_context)s *xc)
+ {
+#if FULL_SYSTEM
+ if((xc->readMiscRegNoEffect(MipsISA::Config) & 0x00000380)==0x80)
+ return true;
+#endif
+ return false;
+ }
}};
def format CP0Control(code, *flags) {{
@@ -138,16 +250,23 @@ def format CP0Control(code, *flags) {{
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = ControlExecute.subst(iop)
+ exec_output = CP0Execute.subst(iop)
+}};
+def format CP0TLB(code, *flags) {{
+ flags += ('IsNonSpeculative', )
+ iop = InstObjParams(name, Name, 'CP0Control', code, flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = ControlTLBExecute.subst(iop)
}};
-
def format CP1Control(code, *flags) {{
flags += ('IsNonSpeculative', )
iop = InstObjParams(name, Name, 'CP1Control', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = ControlExecute.subst(iop)
+ exec_output = CP1Execute.subst(iop)
}};
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index 768f3dd7d..84deeb9db 100755
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -1,32 +1,39 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
+// Brett Miller
////////////////////////////////////////////////////////////////////
//
@@ -177,6 +184,8 @@ def format DspIntOp(code, *opt_flags) {{
code = decl_code + code + write_code
+ opt_flags += ('IsDspOp',)
+
iop = InstObjParams(name, Name, 'DspIntOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
@@ -206,6 +215,8 @@ def format DspHiLoOp(code, *opt_flags) {{
code = decl_code + fetch_code + code + write_code
+ opt_flags += ('IsDspOp',)
+
iop = InstObjParams(name, Name, 'DspHiLoOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff --git a/src/arch/mips/isa/formats/formats.isa b/src/arch/mips/isa/formats/formats.isa
index 1cff9732f..476987d49 100644
--- a/src/arch/mips/isa/formats/formats.isa
+++ b/src/arch/mips/isa/formats/formats.isa
@@ -1,32 +1,38 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
//Templates from this format are used later
//Include the basic format
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 4e81ae2cf..2506e1864 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -1,32 +1,38 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
////////////////////////////////////////////////////////////////////
//
@@ -91,7 +97,10 @@ output exec {{
{
//@TODO: Implement correct CP0 checks to see if the CP1
// unit is enable or not
- return NoFault;
+ if (!isCoprocessorEnabled(xc, 1))
+ return new CoprocessorUnusableFault(1);
+
+ return NoFault;
}
//If any operand is Nan return the appropriate QNaN
@@ -183,6 +192,7 @@ def template FloatingPointExecute {{
%(fp_enable_check)s;
+
//When is the right time to reset cause bits?
//start of every instruction or every cycle?
#if FULL_SYSTEM
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index f23c4cbf6..26adf873f 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -1,32 +1,38 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
////////////////////////////////////////////////////////////////////
//
@@ -119,7 +125,7 @@ output header {{
{
//If Bit 15 is 1 then Sign Extend
int32_t temp = sextImm & 0x00008000;
- if (temp > 0 && strcmp(mnemonic, "lui") != 0) {
+ if (temp > 0 && mnemonic != "lui") {
sextImm |= 0xFFFF0000;
}
}
@@ -313,7 +319,7 @@ output decoder {{
ss << ", ";
}
- if (strcmp(mnemonic, "lui") == 0)
+ if( mnemonic == "lui")
ccprintf(ss, "0x%x ", sextImm);
else
ss << (int) sextImm;
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index 18d1f52f9..ff9970fa1 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -1,33 +1,39 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Steve Reinhardt
-// Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Steve Reinhardt
+// Korey L. Sewell
////////////////////////////////////////////////////////////////////
//
@@ -117,19 +123,19 @@ output exec {{
/** return data in cases where there the size of data is only
known in the packet
*/
- uint64_t getStoreData(%(CPU_exec_context)s *xc, Packet *packet) {
+ uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) {
switch (packet->getSize())
{
- case 8:
+ case 1:
return packet->get<uint8_t>();
- case 16:
+ case 2:
return packet->get<uint16_t>();
- case 32:
+ case 4:
return packet->get<uint32_t>();
- case 864:
+ case 8:
return packet->get<uint64_t>();
default:
@@ -204,6 +210,15 @@ def template MemAccSizeDeclare {{
int memAccSize(%(CPU_exec_context)s *xc);
}};
+
+def template MiscMemAccSize {{
+ int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+ {
+ panic("Misc instruction does not support split access method!");
+ return 0;
+ }
+}};
+
def template EACompConstructor {{
/** TODO: change op_class to AddrGenOp or something (requires
* creating new member of OpClass enum in op_class.hh, updating
@@ -243,7 +258,37 @@ def template EACompExecute {{
Addr EA;
Fault fault = NoFault;
+ if (this->isFloating()) {
+ %(fp_enable_check)s;
+
+ if(fault != NoFault)
+ return fault;
+ }
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ // NOTE: Trace Data is written using execute or completeAcc templates
+ if (fault == NoFault) {
+ xc->setEA(EA);
+ }
+
+ return fault;
+ }
+}};
+
+def template LoadStoreFPEACompExecute {{
+ Fault
+ %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
%(fp_enable_check)s;
+ if(fault != NoFault)
+ return fault;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
@@ -257,14 +302,23 @@ def template EACompExecute {{
}
}};
+
def template LoadMemAccExecute {{
Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
+
Fault fault = NoFault;
+ if (this->isFloating()) {
+ %(fp_enable_check)s;
+
+ if(fault != NoFault)
+ return fault;
+ }
+
%(op_decl)s;
%(op_rd)s;
@@ -288,7 +342,13 @@ def template LoadExecute {{
Addr EA;
Fault fault = NoFault;
- %(fp_enable_check)s;
+ if (this->isFloating()) {
+ %(fp_enable_check)s;
+
+ if(fault != NoFault)
+ return fault;
+ }
+
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
@@ -314,7 +374,13 @@ def template LoadInitiateAcc {{
Addr EA;
Fault fault = NoFault;
- %(fp_enable_check)s;
+ if (this->isFloating()) {
+ %(fp_enable_check)s;
+
+ if(fault != NoFault)
+ return fault;
+ }
+
%(op_src_decl)s;
%(op_rd)s;
%(ea_code)s;
@@ -334,7 +400,13 @@ def template LoadCompleteAcc {{
{
Fault fault = NoFault;
- %(fp_enable_check)s;
+ if (this->isFloating()) {
+ %(fp_enable_check)s;
+
+ if(fault != NoFault)
+ return fault;
+ }
+
%(op_decl)s;
%(op_rd)s;
@@ -353,7 +425,6 @@ def template LoadCompleteAcc {{
}};
-
def template LoadStoreMemAccSize {{
int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
{
@@ -461,6 +532,43 @@ def template StoreExecute {{
}
}};
+
+def template StoreFPExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+ if(fault != NoFault)
+ return fault;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+ memAccessFlags, NULL);
+ if (traceData) { traceData->setData(Mem); }
+ }
+
+ if (fault == NoFault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
def template StoreCondExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
@@ -540,7 +648,31 @@ def template StoreCompleteAcc {{
if (fault == NoFault) {
%(op_wb)s;
- if (traceData) { traceData->setData(getStoreData(xc, pkt)); }
+ if (traceData) { traceData->setData(getMemData(xc, pkt)); }
+ }
+
+ return fault;
+ }
+}};
+
+
+def template StoreCompleteAcc {{
+ Fault %(class_name)s::completeAcc(Packet *pkt,
+ %(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_dest_decl)s;
+
+ if (fault == NoFault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+
+ if (traceData) { traceData->setData(getMemData(xc, pkt)); }
}
return fault;
@@ -650,6 +782,7 @@ def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
exec_template_base = 'Load')
}};
+
def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
@@ -659,6 +792,7 @@ def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
mem_flags = [], inst_flags = []) {{
+ inst_flags += ['IsIndexed']
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
decode_template = ImmNopCheckDecode,
@@ -667,11 +801,30 @@ def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
mem_flags = [], inst_flags = []) {{
+ inst_flags += ['IsIndexed']
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
exec_template_base = 'Store')
}};
+def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
+ mem_flags = [], inst_flags = []) {{
+ inst_flags += ['IsIndexed', 'IsFloating']
+ (header_output, decoder_output, decode_block, exec_output) = \
+ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ decode_template = ImmNopCheckDecode,
+ exec_template_base = 'Load')
+}};
+
+def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
+ mem_flags = [], inst_flags = []) {{
+ inst_flags += ['IsIndexed', 'IsFloating']
+ (header_output, decoder_output, decode_block, exec_output) = \
+ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ exec_template_base = 'Store')
+}};
+
+
def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
mem_flags = [], inst_flags = []) {{
decl_code = 'uint32_t mem_word = Mem.uw;\n'
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index d4c37f812..c7be7fe99 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -1,32 +1,38 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
////////////////////////////////////////////////////////////////////
//
@@ -72,9 +78,9 @@ output decoder {{
{
std::stringstream ss;
- if (strcmp(mnemonic, "mttc0") == 0 || strcmp(mnemonic, "mftc0") == 0) {
+ if (mnemonic == "mttc0" || mnemonic == "mftc0") {
ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
- } else if (strcmp(mnemonic, "mftgpr") == 0) {
+ } else if (mnemonic == "mftgpr") {
ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT);
} else {
ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD);
@@ -96,7 +102,7 @@ output exec {{
void getMTExValues(%(CPU_exec_context)s *xc, unsigned &config3)
{
- config3 = xc->readMiscReg(Config3_MT);
+ config3 = xc->readMiscReg(Config3);
}
}};
@@ -135,7 +141,7 @@ def template ThreadRegisterExecute {{
%(code)s;
}
} else {
- fault = new CoprocessorUnusableFault();
+ fault = new CoprocessorUnusableFault(0);
}
if(fault == NoFault)
@@ -165,7 +171,7 @@ def template MTExecute{{
fault = new ReservedInstructionFault();
}
} else {
- fault = new CoprocessorUnusableFault();
+ fault = new CoprocessorUnusableFault(0);
}
if(fault == NoFault)
diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa
index a8995d658..de5859e2a 100644
--- a/src/arch/mips/isa/formats/noop.isa
+++ b/src/arch/mips/isa/formats/noop.isa
@@ -1,32 +1,38 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
////////////////////////////////////////////////////////////////////
//
diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa
index b6db7864f..a9e880129 100644
--- a/src/arch/mips/isa/formats/tlbop.isa
+++ b/src/arch/mips/isa/formats/tlbop.isa
@@ -1,32 +1,38 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
////////////////////////////////////////////////////////////////////
//
diff --git a/src/arch/mips/isa/formats/trap.isa b/src/arch/mips/isa/formats/trap.isa
index 96d1167d2..ceed14af7 100644
--- a/src/arch/mips/isa/formats/trap.isa
+++ b/src/arch/mips/isa/formats/trap.isa
@@ -1,32 +1,39 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
+// Jaidev Patwardhan
////////////////////////////////////////////////////////////////////
//
@@ -48,6 +55,23 @@ output header {{
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+ class TrapImm : public MipsStaticInst
+ {
+ protected:
+
+ int16_t imm;
+
+ /// Constructor
+ TrapImm(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+
+ };
+
}};
output decoder {{
@@ -55,6 +79,10 @@ output decoder {{
{
return "Disassembly of trap instruction\n";
}
+ std::string TrapImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return "Disassembly of trap instruction\n";
+ }
}};
def template TrapExecute {{
@@ -68,11 +96,23 @@ def template TrapExecute {{
return No_Fault;
}
}};
-
def format Trap(code, *flags) {{
- code = 'warn(\"'
- code += 'Trap Exception Handler Is Currently Not Implemented.'
- code += '\");'
+
+ code ='bool cond;\n' + code
+ code += 'if (cond) {\n'
+ code += 'fault = new TrapFault();\n};'
+
+ iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+def format TrapImm(code, *flags) {{
+
+ code ='bool cond;\n' + code
+ code += 'if (cond) {\n'
+ code += 'fault = new TrapFault();\n};'
iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index 03068fa74..bf91e1fae 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -1,33 +1,39 @@
// -*- mode:c++ -*-
+// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
////////////////////////////////////////////////////////////////////
//
@@ -59,6 +65,57 @@ output header {{
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+ class CP0Unimplemented : public MipsStaticInst
+ {
+ public:
+ /// Constructor
+ CP0Unimplemented(const char *_mnemonic, MachInst _machInst)
+ : MipsStaticInst(_mnemonic, _machInst, No_OpClass)
+ {
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
+ }
+
+ %(BasicExecDeclare)s
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+ class CP1Unimplemented : public MipsStaticInst
+ {
+ public:
+ /// Constructor
+ CP1Unimplemented(const char *_mnemonic, MachInst _machInst)
+ : MipsStaticInst(_mnemonic, _machInst, No_OpClass)
+ {
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
+ }
+
+ %(BasicExecDeclare)s
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+ class CP2Unimplemented : public MipsStaticInst
+ {
+ public:
+ /// Constructor
+ CP2Unimplemented(const char *_mnemonic, MachInst _machInst)
+ : MipsStaticInst(_mnemonic, _machInst, No_OpClass)
+ {
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
+ }
+
+ %(BasicExecDeclare)s
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
/**
* Base class for unimplemented instructions that cause a warning
@@ -101,6 +158,26 @@ output decoder {{
}
std::string
+ CP0Unimplemented::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ return csprintf("%-10s (unimplemented)", mnemonic);
+ }
+
+ std::string
+ CP1Unimplemented::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ return csprintf("%-10s (unimplemented)", mnemonic);
+ }
+ std::string
+ CP2Unimplemented::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ return csprintf("%-10s (unimplemented)", mnemonic);
+ }
+
+ std::string
WarnUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
@@ -120,6 +197,56 @@ output exec {{
}
Fault
+ CP0Unimplemented::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+#if FULL_SYSTEM
+ if (!isCoprocessorEnabled(xc, 0)) {
+ return new CoprocessorUnusableFault(0);
+ }
+ return new ReservedInstructionFault;
+#else
+ panic("attempt to execute unimplemented instruction '%s' "
+ "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
+ inst2string(machInst));
+ return new UnimplementedOpcodeFault;
+#endif
+ }
+
+ Fault
+ CP1Unimplemented::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+#if FULL_SYSTEM
+ if (!isCoprocessorEnabled(xc, 1)) {
+ return new CoprocessorUnusableFault(1);
+ }
+ return new ReservedInstructionFault;
+#else
+ panic("attempt to execute unimplemented instruction '%s' "
+ "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
+ inst2string(machInst));
+ return new UnimplementedOpcodeFault;
+#endif
+ }
+ Fault
+ CP2Unimplemented::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+#if FULL_SYSTEM
+ if (!isCoprocessorEnabled(xc, 2)) {
+ return new CoprocessorUnusableFault(2);
+ }
+ return new ReservedInstructionFault;
+#else
+ panic("attempt to execute unimplemented instruction '%s' "
+ "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
+ inst2string(machInst));
+ return new UnimplementedOpcodeFault;
+#endif
+ }
+
+ Fault
WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@@ -136,8 +263,20 @@ output exec {{
def format FailUnimpl() {{
iop = InstObjParams(name, 'FailUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
-}};
+}};
+def format CP0Unimpl() {{
+ iop = InstObjParams(name, 'CP0Unimplemented')
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+def format CP1Unimpl() {{
+ iop = InstObjParams(name, 'CP1Unimplemented')
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+def format CP2Unimpl() {{
+ iop = InstObjParams(name, 'CP2Unimplemented')
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
def format WarnUnimpl() {{
iop = InstObjParams(name, 'WarnUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
diff --git a/src/arch/mips/isa/formats/unknown.isa b/src/arch/mips/isa/formats/unknown.isa
index 70b3901e9..e4037477f 100644
--- a/src/arch/mips/isa/formats/unknown.isa
+++ b/src/arch/mips/isa/formats/unknown.isa
@@ -72,9 +72,7 @@ output exec {{
Unknown::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- panic("attempt to execute unknown instruction "
- "(inst 0x%08x, opcode 0x%x, binary: %s)", machInst, OPCODE, inst2string(machInst));
- return new UnimplementedOpcodeFault;
+ return new ReservedInstructionFault;
}
}};
diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa
index eea616568..9dac8b571 100644
--- a/src/arch/mips/isa/formats/util.isa
+++ b/src/arch/mips/isa/formats/util.isa
@@ -1,33 +1,39 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Steve Reinhardt
-// Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Steven K. Reinhardt
+// Korey L. Sewell
let {{
def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
@@ -74,6 +80,12 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
fullExecTemplate = eval(exec_template_base + 'Execute')
initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
+ eaCompExecuteTemplate = eval('EACompExecute')
+
+ if (exec_template_base == 'Load' or exec_template_base == 'Store'):
+ memAccSizeTemplate = eval('LoadStoreMemAccSize')
+ else:
+ memAccSizeTemplate = eval('MiscMemAccSize')
# (header_output, decoder_output, decode_block, exec_output)
return (LoadStoreDeclare.subst(iop),
@@ -81,11 +93,12 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ MemAccConstructor.subst(memacc_iop)
+ LoadStoreConstructor.subst(iop),
decode_template.subst(iop),
- EACompExecute.subst(ea_iop)
+ eaCompExecuteTemplate.subst(ea_iop)
+ memAccExecTemplate.subst(memacc_iop)
+ fullExecTemplate.subst(iop)
+ initiateAccTemplate.subst(iop)
- + completeAccTemplate.subst(iop))
+ + completeAccTemplate.subst(iop)
+ + memAccSizeTemplate.subst(memacc_iop))
}};
output header {{
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 0ce807a24..bdd288dd9 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -1,32 +1,38 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
////////////////////////////////////////////////////////////////////
//
@@ -72,7 +78,6 @@ output exec {{
#include "arch/mips/dsp.hh"
#include "arch/mips/pra_constants.hh"
#include "arch/mips/dt_constants.hh"
-#include "arch/mips/mt.hh"
#include "arch/mips/mt_constants.hh"
#include <math.h>
diff --git a/src/arch/mips/isa/main.isa b/src/arch/mips/isa/main.isa
index 2d7c63cd5..de0205b39 100644
--- a/src/arch/mips/isa/main.isa
+++ b/src/arch/mips/isa/main.isa
@@ -1,32 +1,38 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
////////////////////////////////////////////////////////////////////
//
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index b89eb5249..9855ec016 100644
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -1,32 +1,39 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
+// Jaidev Patwardhan
def operand_types {{
'sb' : ('signed int', 8),
@@ -39,7 +46,6 @@ def operand_types {{
'ud' : ('unsigned int', 64),
'sf' : ('float', 32),
'df' : ('float', 64),
- 'qf' : ('float', 128)
}};
def operands {{
@@ -106,9 +112,17 @@ def operands {{
#Status Control Reg
'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1),
+ #LL Flag
+ 'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1),
+
+ # Index Register
+ 'Index':('ControlReg','uw','MipsISA::Index',None,1),
+
+
#Special cases for when a Control Register Access is dependent on
#a combination of bitfield indices (handles MTCO & MFCO)
- 'CP0_RD_SEL': ('ControlReg', 'uw', 'RD << 3 | SEL', None, 1),
+ # Fixed to allow CP0 Register Offset
+ 'CP0_RD_SEL': ('IControlReg', 'uw', '(RD << 3 | SEL) + Ctrl_Base_DepTag', None, 1),
#MT Control Regs
'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1),
@@ -120,10 +134,28 @@ def operands {{
'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1),
'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1),
+ #CP0 Control Regs
+ 'EntryHi': ('ControlReg','uw', 'MipsISA::EntryHi',None,1),
+ 'EntryLo0': ('ControlReg','uw', 'MipsISA::EntryLo0',None,1),
+ 'EntryLo1': ('ControlReg','uw', 'MipsISA::EntryLo1',None,1),
+ 'PageMask': ('ControlReg','uw', 'MipsISA::PageMask',None,1),
+ 'Random': ('ControlReg','uw', 'MipsISA::CP0_Random',None,1),
+ 'ErrorEPC': ('ControlReg','uw', 'MipsISA::ErrorEPC',None,1),
+ 'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1),
+ 'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1),
+ 'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1),
+ 'Config': ('ControlReg','uw', 'MipsISA::Config',None,1),
+ 'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1),
+ 'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1),
+ 'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1),
+ 'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1),
+
+
# named bitfields of Control Regs
'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
+ 'Status_BEV': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
@@ -132,6 +164,24 @@ def operands {{
'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3),
+ 'Config_MT': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 1),
+ 'Config1_CA': ('ControlBitfield', 'uw', 'MipsISA::Config1', None, 1),
+ 'Config3_SP': ('ControlBitfield', 'uw', 'MipsISA::Config3', None, 1),
+ 'PageGrain_ESP': ('ControlBitfield', 'uw', 'MipsISA::PageGrain', None, 1),
+ 'Cause_EXCCODE': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4),
+ 'Cause_TI': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4),
+ 'IntCtl_IPTI': ('ControlBitfield', 'uw', 'MipsISA::IntCtl', None, 4),
+ 'EntryHi_ASID': ('ControlBitfield', 'uw', 'MipsISA::EntryHi', None, 1),
+ 'EntryLo0_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
+ 'EntryLo0_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 3),
+ 'EntryLo0_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
+ 'EntryLo0_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
+ 'EntryLo0_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
+ 'EntryLo1_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
+ 'EntryLo1_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 3),
+ 'EntryLo1_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
+ 'EntryLo1_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
+ 'EntryLo1_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
# named bitfields of Debug Regs
'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1),