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-rw-r--r--src/arch/mips/isa/base.isa7
-rw-r--r--src/arch/mips/isa/decoder.isa44
-rw-r--r--src/arch/mips/isa/formats/branch.isa90
-rw-r--r--src/arch/mips/isa/includes.isa1
-rw-r--r--src/arch/mips/isa/operands.isa3
5 files changed, 92 insertions, 53 deletions
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index 4e2b12fc4..cd6faf0f3 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -56,6 +56,13 @@ output header {{
void printReg(std::ostream &os, int reg) const;
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+ public:
+ void
+ advancePC(MipsISA::PCState &pc) const
+ {
+ pc.advance();
+ }
};
}};
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 9832937b5..3f3bd370a 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -133,25 +133,34 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: jr_hb({{
Config1Reg config1 = Config1;
if (config1.ca == 0) {
- NNPC = Rs;
+ pc.nnpc(Rs);
} else {
panic("MIPS16e not supported\n");
}
+ PCS = pc;
}}, IsReturn, ClearHazards);
default: jr({{
Config1Reg config1 = Config1;
if (config1.ca == 0) {
- NNPC = Rs;
+ pc.nnpc(Rs);
} else {
panic("MIPS16e not supported\n");
}
+ PCS = pc;
}}, IsReturn);
}
0x1: decode HINT {
- 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall
- , ClearHazards);
- default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall);
+ 0x1: jalr_hb({{
+ Rd = pc.nnpc();
+ pc.nnpc(Rs);
+ PCS = pc;
+ }}, IsCall, ClearHazards);
+ default: jalr({{
+ Rd = pc.nnpc();
+ pc.nnpc(Rs);
+ PCS = pc;
+ }}, IsCall);
}
}
@@ -323,9 +332,14 @@ decode OPCODE_HI default Unknown::unknown() {
}
format Jump {
- 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }});
- 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},
- IsCall, Link);
+ 0x2: j({{
+ pc.nnpc((pc.npc() & 0xF0000000) | (JMPTARG << 2));
+ PCS = pc;
+ }});
+ 0x3: jal({{
+ pc.nnpc((pc.npc() & 0xF0000000) | (JMPTARG << 2));
+ PCS = pc;
+ }}, IsCall, Link);
}
format Branch {
@@ -694,15 +708,16 @@ decode OPCODE_HI default Unknown::unknown() {
ConfigReg config = Config;
SRSCtlReg srsCtl = SRSCtl;
DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
+ MipsISA::PCState pc = PCS;
if (status.erl == 1) {
status.erl = 0;
- NPC = ErrorEPC;
+ pc.npc(ErrorEPC);
// Need to adjust NNPC, otherwise things break
- NNPC = ErrorEPC + sizeof(MachInst);
+ pc.nnpc(ErrorEPC + sizeof(MachInst));
} else {
- NPC = EPC;
+ pc.npc(EPC);
// Need to adjust NNPC, otherwise things break
- NNPC = EPC + sizeof(MachInst);
+ pc.nnpc(EPC + sizeof(MachInst));
status.exl = 0;
if (config.ar >=1 &&
srsCtl.hss > 0 &&
@@ -711,6 +726,7 @@ decode OPCODE_HI default Unknown::unknown() {
//xc->setShadowSet(srsCtl.pss);
}
}
+ PCS = pc;
LLFlag = 0;
Status = status;
SRSCtl = srsCtl;
@@ -718,13 +734,15 @@ decode OPCODE_HI default Unknown::unknown() {
0x1F: deret({{
DebugReg debug = Debug;
+ MipsISA::PCState pc = PCS;
if (debug.dm == 1) {
debug.dm = 1;
debug.iexi = 0;
- NPC = DEPC;
+ pc.npc(DEPC);
} else {
// Undefined;
}
+ PCS = pc;
Debug = debug;
}}, IsReturn, IsSerializing, IsERET);
}
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 78f973a70..232a743a7 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -89,7 +89,7 @@ output header {{
}
}
- Addr branchTarget(Addr branchPC) const;
+ MipsISA::PCState branchTarget(const MipsISA::PCState &branchPC) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -116,7 +116,7 @@ output header {{
{
}
- Addr branchTarget(ThreadContext *tc) const;
+ MipsISA::PCState branchTarget(ThreadContext *tc) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -124,17 +124,25 @@ output header {{
}};
output decoder {{
- Addr
- Branch::branchTarget(Addr branchPC) const
+ MipsISA::PCState
+ Branch::branchTarget(const MipsISA::PCState &branchPC) const
{
- return branchPC + 4 + disp;
+ MipsISA::PCState target = branchPC;
+ target.advance();
+ target.npc(branchPC.pc() + sizeof(MachInst) + disp);
+ target.nnpc(target.npc() + sizeof(MachInst));
+ return target;
}
- Addr
+ MipsISA::PCState
Jump::branchTarget(ThreadContext *tc) const
{
- Addr NPC = tc->readNextPC();
- return (NPC & 0xF0000000) | (disp);
+ MipsISA::PCState target = tc->pcState();
+ Addr pc = target.pc();
+ target.advance();
+ target.npc((pc & 0xF0000000) | disp);
+ target.nnpc(target.npc() + sizeof(MachInst));
+ return target;
}
const std::string &
@@ -217,19 +225,16 @@ output decoder {{
}};
def format Branch(code, *opt_flags) {{
- not_taken_code = ' NNPC = NNPC;\n'
- not_taken_code += '} \n'
+ not_taken_code = ''
#Build Instruction Flags
#Use Link & Likely Flags to Add Link/Condition Code
inst_flags = ('IsDirectControl', )
for x in opt_flags:
if x == 'Link':
- code += 'R31 = NNPC;\n'
+ code += 'R31 = pc.nnpc();\n'
elif x == 'Likely':
- not_taken_code = ' NPC = NNPC;\n'
- not_taken_code += ' NNPC = NNPC + 4;\n'
- not_taken_code += '} \n'
+ not_taken_code = 'pc.advance();'
inst_flags += ('IsCondDelaySlot', )
else:
inst_flags += (x, )
@@ -241,11 +246,17 @@ def format Branch(code, *opt_flags) {{
inst_flags += ('IsCondControl', )
#Condition code
- code = 'bool cond;\n' + code
- code += 'if (cond) {\n'
- code += ' NNPC = NPC + disp;\n'
- code += '} else {\n'
- code += not_taken_code
+ code = '''
+ bool cond;
+ MipsISA::PCState pc = PCS;
+ %(code)s
+ if (cond) {
+ pc.nnpc(pc.npc() + disp);
+ } else {
+ %(not_taken_code)s
+ }
+ PCS = pc;
+ ''' % { "code" : code, "not_taken_code" : not_taken_code }
iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
header_output = BasicDeclare.subst(iop)
@@ -255,19 +266,16 @@ def format Branch(code, *opt_flags) {{
}};
def format DspBranch(code, *opt_flags) {{
- not_taken_code = ' NNPC = NNPC;\n'
- not_taken_code += '} \n'
+ not_taken_code = ''
#Build Instruction Flags
#Use Link & Likely Flags to Add Link/Condition Code
inst_flags = ('IsDirectControl', )
for x in opt_flags:
if x == 'Link':
- code += 'R31 = NNPC;\n'
+ code += 'R32 = pc.nnpc();'
elif x == 'Likely':
- not_taken_code = ' NPC = NNPC;\n'
- not_taken_code += ' NNPC = NNPC + 4;\n'
- not_taken_code += '} \n'
+ not_taken_code = 'pc.advance();'
inst_flags += ('IsCondDelaySlot', )
else:
inst_flags += (x, )
@@ -278,19 +286,19 @@ def format DspBranch(code, *opt_flags) {{
else:
inst_flags += ('IsCondControl', )
- #Declaration code
- decl_code = 'bool cond;\n'
- decl_code += 'uint32_t dspctl;\n'
-
- #Fetch code
- fetch_code = 'dspctl = DSPControl;\n'
-
#Condition code
- code = decl_code + fetch_code + code
- code += 'if (cond) {\n'
- code += ' NNPC = NPC + disp;\n'
- code += '} else {\n'
- code += not_taken_code
+ code = '''
+ MipsISA::PCState pc = PCS;
+ bool cond;
+ uint32_t dspctl = DSPControl;
+ %(code)s
+ if (cond) {
+ pc.nnpc(pc.npc() + disp);
+ } else {
+ %(not_taken_code)s
+ }
+ PCS = pc;
+ ''' % { "code" : code, "not_taken_code" : not_taken_code }
iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
header_output = BasicDeclare.subst(iop)
@@ -305,12 +313,18 @@ def format Jump(code, *opt_flags) {{
inst_flags = ('IsIndirectControl', 'IsUncondControl')
for x in opt_flags:
if x == 'Link':
- code = 'R31 = NNPC;\n' + code
+ code = '''
+ R31 = pc.nnpc();
+ ''' + code
elif x == 'ClearHazards':
code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
else:
inst_flags += (x, )
+ code = '''
+ MipsISA::PCState pc = PCS;
+ ''' + code
+
iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 22eb3bf13..d5e1448ac 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -39,6 +39,7 @@ output header {{
#include <iomanip>
#include "arch/mips/isa_traits.hh"
+#include "arch/mips/types.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
}};
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index 27cb4357a..1bb5ae5b3 100644
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -151,6 +151,5 @@ def operands {{
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
#Program Counter Operands
- 'NPC': ('NPC', 'uw', None, 'IsControl', 4),
- 'NNPC':('NNPC', 'uw', None, 'IsControl', 4)
+ 'PCS': ('PCState', 'uw', None, (None, None, 'IsControl'), 4)
}};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 15:56:45 +0000