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Diffstat (limited to 'src/arch/mips/isa')
| -rw-r--r-- | src/arch/mips/isa/operands.isa | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa index 609708a13..c2733be9d 100644 --- a/src/arch/mips/isa/operands.isa +++ b/src/arch/mips/isa/operands.isa @@ -113,10 +113,7 @@ def operands {{ 'Index':('ControlReg','uw','MipsISA::Index',None,1), - #Special cases for when a Control Register Access is dependent on - #a combination of bitfield indices (handles MTCO & MFCO) - # Fixed to allow CP0 Register Offset - 'CP0_RD_SEL': ('IControlReg', 'uw', '(RD << 3 | SEL) + Ctrl_Base_DepTag', None, 1), + 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1), #MT Control Regs 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1), |