summaryrefslogtreecommitdiff
path: root/src/arch/mips/isa
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/mips/isa')
-rw-r--r--src/arch/mips/isa/base.isa10
-rw-r--r--src/arch/mips/isa/decoder.isa181
-rw-r--r--src/arch/mips/isa/formats/int.isa12
-rw-r--r--src/arch/mips/isa/formats/mt.isa3
4 files changed, 128 insertions, 78 deletions
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index 455ed70e7..c0f259666 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -53,7 +53,7 @@ output header {{
/// Print a register name for disassembly given the unique
/// dependence tag number (FP or int).
- void printReg(std::ostream &os, int reg) const;
+ void printReg(std::ostream &os, RegId reg) const;
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -70,13 +70,13 @@ output header {{
//Ouputs to decoder.cc
output decoder {{
- void MipsStaticInst::printReg(std::ostream &os, int reg) const
+ void MipsStaticInst::printReg(std::ostream &os, RegId reg) const
{
- if (reg < FP_Reg_Base) {
- ccprintf(os, "r%d", reg);
+ if (reg.regClass == IntRegClass) {
+ ccprintf(os, "r%d", reg.regIdx);
}
else {
- ccprintf(os, "f%d", reg - FP_Reg_Base);
+ ccprintf(os, "f%d", reg.regIdx);
}
}
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 5c3c6f6b1..a349f1a05 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -384,44 +384,86 @@ decode OPCODE_HI default Unknown::unknown() {
// Decode MIPS MT MFTR instruction into sub-instructions
0x8: decode MT_U {
0x0: mftc0({{
- data = xc->readRegOtherThread((RT << 3 | SEL) +
- Misc_Reg_Base);
+ data = xc->readRegOtherThread(RegId(MiscRegClass,
+ (RT << 3 | SEL)));
}});
0x1: decode SEL {
0x0: mftgpr({{
- data = xc->readRegOtherThread(RT);
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, RT));
}});
0x1: decode RT {
- 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }});
- 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }});
- 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }});
- 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }});
- 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }});
- 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }});
- 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }});
- 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }});
- 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }});
- 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }});
- 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }});
- 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }});
- 0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }});
+ 0x0: mftlo_dsp0({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO0));
+ }});
+ 0x1: mfthi_dsp0({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI0));
+ }});
+ 0x2: mftacx_dsp0({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX0));
+ }});
+ 0x4: mftlo_dsp1({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO1));
+ }});
+ 0x5: mfthi_dsp1({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI1));
+ }});
+ 0x6: mftacx_dsp1({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX1));
+ }});
+ 0x8: mftlo_dsp2({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO2));
+ }});
+ 0x9: mfthi_dsp2({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI2));
+ }});
+ 0x10: mftacx_dsp2({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX2));
+ }});
+ 0x12: mftlo_dsp3({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO3));
+ }});
+ 0x13: mfthi_dsp3({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI3));
+ }});
+ 0x14: mftacx_dsp3({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX3));
+ }});
+ 0x16: mftdsp({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_CONTROL));
+ }});
default: CP0Unimpl::unknown();
}
0x2: decode MT_H {
- 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
- FP_Reg_Base);
+ 0x0: mftc1({{
+ data = xc->readRegOtherThread(
+ RegId(FloatRegClass, RT));
}});
- 0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
- FP_Reg_Base);
+ 0x1: mfthc1({{
+ data = xc->readRegOtherThread(
+ RegId(FloatRegClass, RT));
}});
}
0x3: cftc1({{
- uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR +
- FP_Reg_Base);
+ uint32_t fcsr_val = xc->readRegOtherThread(
+ RegId(FloatRegClass, FLOATREG_FCSR));
switch (RT) {
case 0:
- data = xc->readRegOtherThread(FLOATREG_FIR +
- Misc_Reg_Base);
+ data = xc->readRegOtherThread(
+ RegId(MiscRegClass, FLOATREG_FIR));
break;
case 25:
data = (fcsr_val & 0xFE000000 >> 24) |
@@ -450,56 +492,62 @@ decode OPCODE_HI default Unknown::unknown() {
format MT_MTTR {
// Decode MIPS MT MTTR instruction into sub-instructions
0xC: decode MT_U {
- 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Misc_Reg_Base,
- Rt);
+ 0x0: mttc0({{ xc->setRegOtherThread(
+ RegId(MiscRegClass, (RD << 3 | SEL)), Rt);
}});
0x1: decode SEL {
- 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }});
+ 0x0: mttgpr({{ xc->setRegOtherThread(
+ RegId(IntRegClass, RD), Rt);
+ }});
0x1: decode RT {
- 0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt);
- }});
- 0x1: mtthi_dsp0({{ xc->setRegOtherThread(INTREG_DSP_HI0,
- Rt);
- }});
- 0x2: mttacx_dsp0({{ xc->setRegOtherThread(INTREG_DSP_ACX0,
- Rt);
- }});
- 0x4: mttlo_dsp1({{ xc->setRegOtherThread(INTREG_DSP_LO1,
- Rt);
- }});
- 0x5: mtthi_dsp1({{ xc->setRegOtherThread(INTREG_DSP_HI1,
- Rt);
- }});
- 0x6: mttacx_dsp1({{ xc->setRegOtherThread(INTREG_DSP_ACX1,
- Rt);
- }});
- 0x8: mttlo_dsp2({{ xc->setRegOtherThread(INTREG_DSP_LO2,
- Rt);
- }});
- 0x9: mtthi_dsp2({{ xc->setRegOtherThread(INTREG_DSP_HI2,
- Rt);
- }});
- 0x10: mttacx_dsp2({{ xc->setRegOtherThread(INTREG_DSP_ACX2,
- Rt);
- }});
- 0x12: mttlo_dsp3({{ xc->setRegOtherThread(INTREG_DSP_LO3,
- Rt);
- }});
- 0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3,
- Rt);
- }});
- 0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt);
- }});
- 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }});
+ 0x0: mttlo_dsp0({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO0), Rt);
+ }});
+ 0x1: mtthi_dsp0({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI0), Rt);
+ }});
+ 0x2: mttacx_dsp0({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX0), Rt);
+ }});
+ 0x4: mttlo_dsp1({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO1), Rt);
+ }});
+ 0x5: mtthi_dsp1({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI1), Rt);
+ }});
+ 0x6: mttacx_dsp1({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX1), Rt);
+ }});
+ 0x8: mttlo_dsp2({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO2), Rt);
+ }});
+ 0x9: mtthi_dsp2({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI2), Rt);
+ }});
+ 0x10: mttacx_dsp2({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX2), Rt);
+ }});
+ 0x12: mttlo_dsp3({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO3), Rt);
+ }});
+ 0x13: mtthi_dsp3({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI3), Rt);
+ }});
+ 0x14: mttacx_dsp3({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX3), Rt);
+ }});
+ 0x16: mttdsp({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_CONTROL), Rt);
+ }});
default: CP0Unimpl::unknown();
}
0x2: mttc1({{
- uint64_t data = xc->readRegOtherThread(RD +
- FP_Reg_Base);
+ uint64_t data = xc->readRegOtherThread(
+ RegId(FloatRegClass, RD));
data = insertBits(data, MT_H ? 63 : 31,
MT_H ? 32 : 0, Rt);
- xc->setRegOtherThread(RD + FP_Reg_Base,
+ xc->setRegOtherThread(RegId(FloatRegClass, RD),
data);
}});
0x3: cttc1({{
@@ -534,7 +582,8 @@ decode OPCODE_HI default Unknown::unknown() {
"Access to Floating Control "
"S""tatus Register", FS);
}
- xc->setRegOtherThread(FLOATREG_FCSR + FP_Reg_Base, data);
+ xc->setRegOtherThread(
+ RegId(FloatRegClass, FLOATREG_FCSR), data);
}});
default: CP0Unimpl::unknown();
}
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index 52358bbdb..641608e89 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -257,9 +257,9 @@ output decoder {{
ccprintf(ss, "%-10s ", mnemonic);
- if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
+ if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
printReg(ss, _destRegIdx[0]);
- } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
+ } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
printReg(ss, _srcRegIdx[0]);
}
@@ -272,9 +272,9 @@ output decoder {{
ccprintf(ss, "%-10s ", mnemonic);
- if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
+ if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
printReg(ss, _destRegIdx[0]);
- } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
+ } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
printReg(ss, _srcRegIdx[0]);
}
@@ -287,9 +287,9 @@ output decoder {{
ccprintf(ss, "%-10s ", mnemonic);
- if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
+ if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
printReg(ss, _destRegIdx[0]);
- } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
+ } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
printReg(ss, _srcRegIdx[0]);
}
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 8d2254cb4..b34773ef5 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -102,7 +102,8 @@ output exec {{
MVPConf0Reg &mvp_conf0)
{
vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
- tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base);
+ tc_bind_mt = xc->readRegOtherThread(RegId(MiscRegClass,
+ MISCREG_TC_BIND));
tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 00:41:47 +0000