diff options
Diffstat (limited to 'src/arch/mips/isa')
| -rw-r--r-- | src/arch/mips/isa/decoder.isa | 58 | ||||
| -rw-r--r-- | src/arch/mips/isa/formats/control.isa | 10 | ||||
| -rwxr-xr-x | src/arch/mips/isa/formats/dsp.isa | 4 | ||||
| -rw-r--r-- | src/arch/mips/isa/formats/fp.isa | 9 | ||||
| -rw-r--r-- | src/arch/mips/isa/formats/mt.isa | 12 | ||||
| -rw-r--r-- | src/arch/mips/isa/operands.isa | 103 |
6 files changed, 99 insertions, 97 deletions
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 60bc15513..f8cdb920b 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -406,19 +406,19 @@ decode OPCODE_HI default Unknown::unknown() { 0x1: decode SEL { 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }}); 0x1: decode RT { - 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }}); - 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }}); - 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }}); - 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }}); - 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }}); - 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }}); - 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }}); - 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }}); - 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }}); - 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }}); - 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }}); - 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }}); - 0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }}); + 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }}); + 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }}); + 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }}); + 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }}); + 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }}); + 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }}); + 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }}); + 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }}); + 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }}); + 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }}); + 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }}); + 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }}); + 0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }}); default: CP0Unimpl::unknown(); } 0x2: decode MT_H { @@ -429,12 +429,12 @@ decode OPCODE_HI default Unknown::unknown() { FP_Base_DepTag); }}); } - 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR + + 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag); switch (RT) { case 0: - data = xc->readRegOtherThread(MipsISA::FIR + + data = xc->readRegOtherThread(FLOATREG_FIR + Ctrl_Base_DepTag); break; case 25: @@ -469,41 +469,41 @@ decode OPCODE_HI default Unknown::unknown() { 0x1: decode SEL { 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }}); 0x1: decode RT { - 0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt); + 0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt); }}); - 0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0, + 0x1: mtthi_dsp0({{ xc->setRegOtherThread(INTREG_DSP_HI0, Rt); }}); - 0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0, + 0x2: mttacx_dsp0({{ xc->setRegOtherThread(INTREG_DSP_ACX0, Rt); }}); - 0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1, + 0x4: mttlo_dsp1({{ xc->setRegOtherThread(INTREG_DSP_LO1, Rt); }}); - 0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1, + 0x5: mtthi_dsp1({{ xc->setRegOtherThread(INTREG_DSP_HI1, Rt); }}); - 0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1, + 0x6: mttacx_dsp1({{ xc->setRegOtherThread(INTREG_DSP_ACX1, Rt); }}); - 0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2, + 0x8: mttlo_dsp2({{ xc->setRegOtherThread(INTREG_DSP_LO2, Rt); }}); - 0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2, + 0x9: mtthi_dsp2({{ xc->setRegOtherThread(INTREG_DSP_HI2, Rt); }}); - 0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2, + 0x10: mttacx_dsp2({{ xc->setRegOtherThread(INTREG_DSP_ACX2, Rt); }}); - 0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3, + 0x12: mttlo_dsp3({{ xc->setRegOtherThread(INTREG_DSP_LO3, Rt); }}); - 0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3, + 0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3, Rt); }}); - 0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt); + 0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt); }}); - 0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }}); + 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }}); default: CP0Unimpl::unknown(); } @@ -546,7 +546,7 @@ decode OPCODE_HI default Unknown::unknown() { panic("FP Control Value (%d) Not Available. Ignoring Access to" "Floating Control Status Register", FS); } - xc->setRegOtherThread(FCSR, data); + xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); }}); default: CP0Unimpl::unknown(); } diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa index c8eddb1ad..cb5b4372f 100644 --- a/src/arch/mips/isa/formats/control.isa +++ b/src/arch/mips/isa/formats/control.isa @@ -180,12 +180,12 @@ output exec {{ #if !FULL_SYSTEM return true; #else - MiscReg Stat = xc->readMiscReg(MipsISA::Status); + MiscReg Stat = xc->readMiscReg(MISCREG_STATUS); switch(cop_num) { case 0: { - MiscReg Dbg = xc->readMiscReg(MipsISA::Debug); + MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG); if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode @@ -216,8 +216,8 @@ output exec {{ bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc) { #if FULL_SYSTEM - MiscReg Stat = xc->readMiscRegNoEffect(MipsISA::Status); - MiscReg Dbg = xc->readMiscRegNoEffect(MipsISA::Debug); + MiscReg Stat = xc->readMiscRegNoEffect(MISCREG_STATUS); + MiscReg Dbg = xc->readMiscRegNoEffect(MISCREG_DEBUG); if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode @@ -232,7 +232,7 @@ output exec {{ bool isMMUTLB(%(CPU_exec_context)s *xc) { #if FULL_SYSTEM - if((xc->readMiscRegNoEffect(MipsISA::Config) & 0x00000380)==0x80) + if((xc->readMiscRegNoEffect(MISCREG_CONFIG) & 0x00000380)==0x80) return true; #endif return false; diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa index 1874d37b2..7d16b4162 100755 --- a/src/arch/mips/isa/formats/dsp.isa +++ b/src/arch/mips/isa/formats/dsp.isa @@ -143,7 +143,7 @@ output exec {{ bool isDspEnabled(%(CPU_exec_context)s *xc) { #if FULL_SYSTEM - if( bits( xc->readMiscReg(MipsISA::Status), 24, 24 ) == 0 ) + if( bits( xc->readMiscReg(MISCREG_STATUS), 24, 24 ) == 0 ) return false; #else //printf("Syscall Emulation Mode: isDspEnabled() check defaults to TRUE\n"); @@ -156,7 +156,7 @@ output exec {{ bool isDspPresent(%(CPU_exec_context)s *xc) { #if FULL_SYSTEM - if( bits( xc->readMiscReg(MipsISA::Config3), 10, 10 ) == 0 ) + if( bits( xc->readMiscReg(MISCREG_CONFIG3), 10, 10 ) == 0 ) return false; #else //printf("Syscall Emulation Mode: isDspPresent() check defaults to TRUE\n"); diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index 52fcd0724..72d87f997 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -135,12 +135,13 @@ output exec {{ cpu->setFloatRegOperandBits(inst, 0, mips_nan); //Read FCSR from FloatRegFile - uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); + uint32_t fcsr_bits = + cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); uint32_t new_fcsr = genInvalidVector(fcsr_bits); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr); + cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr); if (traceData) { traceData->setData(mips_nan); } return true; @@ -153,13 +154,13 @@ output exec {{ fpResetCauseBits(%(CPU_exec_context)s *cpu) { //Read FCSR from FloatRegFile - uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR); + uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); // TODO: Use utility function here fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FCSR, fcsr); + cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr); } }}; diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa index 4f2d33709..9d354c46a 100644 --- a/src/arch/mips/isa/formats/mt.isa +++ b/src/arch/mips/isa/formats/mt.isa @@ -90,16 +90,16 @@ output exec {{ TCBindReg &tc_bind, VPEControlReg &vpe_control, MVPConf0Reg &mvp_conf0) { - vpe_conf0 = xc->readMiscReg(VPEConf0); - tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag); - tc_bind = xc->readMiscReg(TCBind); - vpe_control = xc->readMiscReg(VPEControl); - mvp_conf0 = xc->readMiscReg(MVPConf0); + vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0); + tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag); + tc_bind = xc->readMiscReg(MISCREG_TC_BIND); + vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL); + mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0); } void getMTExValues(%(CPU_exec_context)s *xc, Config3Reg &config3) { - config3 = xc->readMiscReg(Config3); + config3 = xc->readMiscReg(MISCREG_CONFIG3); } }}; diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa index 1af8857cc..50726cd30 100644 --- a/src/arch/mips/isa/operands.isa +++ b/src/arch/mips/isa/operands.isa @@ -56,29 +56,29 @@ def operands {{ 'R2': ('IntReg', 'uw','2', 'IsInteger', 5), #Special Integer Reg operands - 'LO0': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 6), - 'HI0': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 7), + 'LO0': ('IntReg', 'uw','INTREG_LO', 'IsInteger', 6), + 'HI0': ('IntReg', 'uw','INTREG_HI', 'IsInteger', 7), #Bitfield-dependent HI/LO Register Access - 'LO_RD_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACDST*3', None, 6), - 'HI_RD_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACDST*3', None, 7), - 'LO_RS_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACSRC*3', None, 6), - 'HI_RS_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACSRC*3', None, 7), + 'LO_RD_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACDST*3', None, 6), + 'HI_RD_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACDST*3', None, 7), + 'LO_RS_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACSRC*3', None, 6), + 'HI_RS_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACSRC*3', None, 7), #DSP Special Purpose Integer Operands - 'DSPControl': ('IntReg', 'uw', 'MipsISA::DSPControl', None, 8), - 'DSPLo0': ('IntReg', 'uw', 'MipsISA::LO', None, 1), - 'DSPHi0': ('IntReg', 'uw', 'MipsISA::HI', None, 1), - 'DSPACX0': ('IntReg', 'uw', 'MipsISA::DSPACX0', None, 1), - 'DSPLo1': ('IntReg', 'uw', 'MipsISA::DSPLo1', None, 1), - 'DSPHi1': ('IntReg', 'uw', 'MipsISA::DSPHi1', None, 1), - 'DSPACX1': ('IntReg', 'uw', 'MipsISA::DSPACX1', None, 1), - 'DSPLo2': ('IntReg', 'uw', 'MipsISA::DSPLo2', None, 1), - 'DSPHi2': ('IntReg', 'uw', 'MipsISA::DSPHi2', None, 1), - 'DSPACX2': ('IntReg', 'uw', 'MipsISA::DSPACX2', None, 1), - 'DSPLo3': ('IntReg', 'uw', 'MipsISA::DSPLo3', None, 1), - 'DSPHi3': ('IntReg', 'uw', 'MipsISA::DSPHi3', None, 1), - 'DSPACX3': ('IntReg', 'uw', 'MipsISA::DSPACX3', None, 1), + 'DSPControl': ('IntReg', 'uw', 'INTREG_DSP_CONTROL', None, 8), + 'DSPLo0': ('IntReg', 'uw', 'INTREG_LO', None, 1), + 'DSPHi0': ('IntReg', 'uw', 'INTREG_HI', None, 1), + 'DSPACX0': ('IntReg', 'uw', 'INTREG_DSP_ACX0', None, 1), + 'DSPLo1': ('IntReg', 'uw', 'INTREG_DSP_LO1', None, 1), + 'DSPHi1': ('IntReg', 'uw', 'INTREG_DSP_HI1', None, 1), + 'DSPACX1': ('IntReg', 'uw', 'INTREG_DSP_ACX1', None, 1), + 'DSPLo2': ('IntReg', 'uw', 'INTREG_DSP_LO2', None, 1), + 'DSPHi2': ('IntReg', 'uw', 'INTREG_DSP_HI2', None, 1), + 'DSPACX2': ('IntReg', 'uw', 'INTREG_DSP_ACX2', None, 1), + 'DSPLo3': ('IntReg', 'uw', 'INTREG_DSP_LO3', None, 1), + 'DSPHi3': ('IntReg', 'uw', 'INTREG_DSP_HI3', None, 1), + 'DSPACX3': ('IntReg', 'uw', 'INTREG_DSP_ACX3', None, 1), #Floating Point Reg Operands 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1), @@ -87,11 +87,11 @@ def operands {{ 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3), #Special Purpose Floating Point Control Reg Operands - 'FIR': ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1), - 'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2), - 'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3), - 'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3), - 'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3), + 'FIR': ('FloatReg', 'uw', 'FLOATREG_FIR', 'IsFloating', 1), + 'FCCR': ('FloatReg', 'uw', 'FLOATREG_FCCR', 'IsFloating', 2), + 'FEXR': ('FloatReg', 'uw', 'FLOATREG_FEXR', 'IsFloating', 3), + 'FENR': ('FloatReg', 'uw', 'FLOATREG_FENR', 'IsFloating', 3), + 'FCSR': ('FloatReg', 'uw', 'FLOATREG_FCSR', 'IsFloating', 3), #Operands For Paired Singles FP Operations 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4), @@ -104,44 +104,45 @@ def operands {{ 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7), #Status Control Reg - 'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1), + 'Status': ('ControlReg', 'uw', 'MISCREG_STATUS', None, 1), #LL Flag - 'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1), + 'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1), # Index Register - 'Index':('ControlReg','uw','MipsISA::Index',None,1), + 'Index':('ControlReg','uw','MISCREG_INDEX',None,1), 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1), #MT Control Regs - 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1), - 'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1), - 'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1), - 'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1), - 'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1), - 'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1), - 'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1), - 'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1), + 'MVPConf0': ('ControlReg', 'uw', 'MISCREG_MVP_CONF0', None, 1), + 'MVPControl': ('ControlReg', 'uw', 'MISCREG_MVP_CONTROL', None, 1), + 'TCBind': ('ControlReg', 'uw', 'MISCREG_TC_BIND', None, 1), + 'TCStatus': ('ControlReg', 'uw', 'MISCREG_TC_STATUS', None, 1), + 'TCRestart': ('ControlReg', 'uw', 'MISCREG_TC_RESTART', None, 1), + 'VPEConf0': ('ControlReg', 'uw', 'MISCREG_VPE_CONF0', None, 1), + 'VPEControl': ('ControlReg', 'uw', 'MISCREG_VPE_CONTROL', None, 1), + 'YQMask': ('ControlReg', 'uw', 'MISCREG_YQMASK', None, 1), #CP0 Control Regs - 'EntryHi': ('ControlReg','uw', 'MipsISA::EntryHi',None,1), - 'EntryLo0': ('ControlReg','uw', 'MipsISA::EntryLo0',None,1), - 'EntryLo1': ('ControlReg','uw', 'MipsISA::EntryLo1',None,1), - 'PageMask': ('ControlReg','uw', 'MipsISA::PageMask',None,1), - 'Random': ('ControlReg','uw', 'MipsISA::CP0_Random',None,1), - 'ErrorEPC': ('ControlReg','uw', 'MipsISA::ErrorEPC',None,1), - 'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1), - 'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1), - 'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1), - 'Config': ('ControlReg','uw', 'MipsISA::Config',None,1), - 'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1), - 'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1), - 'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1), - 'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1), - 'Debug': ('ControlReg','uw', 'MipsISA::Debug',None,1), - 'Cause': ('ControlReg','uw', 'MipsISA::Cause',None,1), + 'EntryHi': ('ControlReg','uw', 'MISCREG_ENTRYHI',None,1), + 'EntryLo0': ('ControlReg','uw', 'MISCREG_ENTRYLO0',None,1), + 'EntryLo1': ('ControlReg','uw', 'MISCREG_ENTRYLO1',None,1), + 'PageMask': ('ControlReg','uw', 'MISCREG_PAGEMASK',None,1), + 'Random': ('ControlReg','uw', 'MISCREG_CP0_RANDOM',None,1), + 'ErrorEPC': ('ControlReg','uw', 'MISCREG_ERROR_EPC',None,1), + 'EPC': ('ControlReg','uw', 'MISCREG_EPC',None,1), + 'DEPC': ('ControlReg','uw', 'MISCREG_DEPC',None,1), + 'IntCtl': ('ControlReg','uw', 'MISCREG_INTCTL',None,1), + 'SRSCtl': ('ControlReg','uw', 'MISCREG_SRSCTL',None,1), + 'Config': ('ControlReg','uw', 'MISCREG_CONFIG',None,1), + 'Config3': ('ControlReg','uw', 'MISCREG_CONFIG3',None,1), + 'Config1': ('ControlReg','uw', 'MISCREG_CONFIG1',None,1), + 'Config2': ('ControlReg','uw', 'MISCREG_CONFIG2',None,1), + 'PageGrain': ('ControlReg','uw', 'MISCREG_PAGEGRAIN',None,1), + 'Debug': ('ControlReg','uw', 'MISCREG_DEBUG',None,1), + 'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1), #Memory Operand 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), |