diff options
Diffstat (limited to 'src/arch/mips/locked_mem.hh')
| -rw-r--r-- | src/arch/mips/locked_mem.hh | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh index e202a11aa..3c81bc249 100644 --- a/src/arch/mips/locked_mem.hh +++ b/src/arch/mips/locked_mem.hh @@ -45,17 +45,18 @@ namespace MipsISA { + template <class XC> inline void handleLockedRead(XC *xc, Request *req) { xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf); xc->setMiscRegNoEffect(LLFlag, true); - DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n", + DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link" + " Address set to %x.\n", req->threadId(), req->getPaddr() & ~0xf); } - template <class XC> inline bool handleLockedWrite(XC *xc, Request *req) @@ -89,14 +90,17 @@ handleLockedWrite(XC *xc, Request *req) } if (stCondFailures == 5000) { - panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n"); + panic("Max (5000) Store Conditional Fails Reached. " + "Check Code For Deadlock.\n"); } if (!lock_flag){ - DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n", + DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, " + "Store Conditional Failed.\n", req->threadId()); } else if ((req->getPaddr() & ~0xf) != lock_addr) { - DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n", + DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, " + "Store Conditional Failed.\n", req->threadId()); } // store conditional failed already, so don't issue it to mem @@ -107,7 +111,6 @@ handleLockedWrite(XC *xc, Request *req) return true; } - } // namespace MipsISA #endif |