diff options
Diffstat (limited to 'src/arch/mips/mt.hh')
| -rwxr-xr-x | src/arch/mips/mt.hh | 185 |
1 files changed, 77 insertions, 108 deletions
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh index b581d5cf0..a6363e191 100755 --- a/src/arch/mips/mt.hh +++ b/src/arch/mips/mt.hh @@ -40,6 +40,7 @@ #include "arch/mips/faults.hh" #include "arch/mips/isa_traits.hh" #include "arch/mips/mt_constants.hh" +#include "arch/mips/pra_constants.hh" #include "arch/mips/registers.hh" #include "base/bitfield.hh" #include "base/trace.hh" @@ -50,21 +51,20 @@ namespace MipsISA { - template <class TC> inline unsigned getVirtProcNum(TC *tc) { - MiscReg tcbind = tc->readMiscRegNoEffect(TCBind); - return bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO); + TCBindReg tcbind = tc->readMiscRegNoEffect(TCBind); + return tcbind.curVPE; } template <class TC> inline unsigned getTargetThread(TC *tc) { - MiscReg vpec_ctrl = tc->readMiscRegNoEffect(VPEControl); - return bits(vpec_ctrl, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO); + VPEControlReg vpeCtrl = tc->readMiscRegNoEffect(VPEControl); + return vpeCtrl.targTC; } template <class TC> @@ -75,11 +75,13 @@ haltThread(TC *tc) tc->halt(); // Save last known PC in TCRestart - // @TODO: Needs to check if this is a branch and if so, take previous instruction + // @TODO: Needs to check if this is a branch and if so, + // take previous instruction tc->setMiscReg(TCRestart, tc->readNextPC()); - warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->threadId(), tc->getCpuPtr()->name(), - tc->readPC(), tc->readNextPC()); + warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", + curTick, tc->threadId(), tc->getCpuPtr()->name(), + tc->readPC(), tc->readNextPC()); } } @@ -92,14 +94,14 @@ restoreThread(TC *tc) IntReg pc = tc->readMiscRegNoEffect(TCRestart); // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY - // tc->setPCEvent(pc, pc + 4, pc + 8); tc->setPC(pc); tc->setNextPC(pc + 4); tc->setNextNPC(pc + 8); tc->activate(0); - warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->threadId(), tc->getCpuPtr()->name(), - tc->readPC()); + warn("%i: Restoring thread %i in %s @ PC %x", + curTick, tc->threadId(), tc->getCpuPtr()->name(), + tc->readPC()); } } @@ -107,58 +109,48 @@ template <class TC> void forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt) { - int num_threads = bits(tc->readMiscRegNoEffect(MVPConf0), MVPC0_PTC_HI, MVPC0_PTC_LO) + 1; + MVPConf0Reg mvpConf = tc->readMiscRegNoEffect(MVPConf0); + int num_threads = mvpConf.ptc + 1; int success = 0; for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) { - unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag, - tid); - unsigned tc_bind = tc->readMiscRegNoEffect(MipsISA::TCBind); - - if (bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) == - bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) { + TCBindReg tidTCBind = + tc->readRegOtherThread(TCBind + Ctrl_Base_DepTag, tid); + TCBindReg tcBind = tc->readMiscRegNoEffect(TCBind); - unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag, - tid); + if (tidTCBind.curVPE = tcBind.curVPE) { - unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag, - tid); + TCStatusReg tidTCStatus = + tc->readRegOtherThread(TCStatus + Ctrl_Base_DepTag,tid); - if (bits(tid_TCStatus, TCS_DA) == 1 && - bits(tid_TCHalt, TCH_H) == 0 && - bits(tid_TCStatus, TCS_A) == 0 && - success == 0) { + TCHaltReg tidTCHalt = + tc->readRegOtherThread(TCHalt + Ctrl_Base_DepTag,tid); - tc->setRegOtherThread(MipsISA::TCRestart + Ctrl_Base_DepTag, Rs, tid); + if (tidTCStatus.da == 1 && tidTCHalt.h == 0 && + tidTCStatus.a == 0 && success == 0) { + tc->setRegOtherThread(TCRestart + Ctrl_Base_DepTag, Rs, tid); tc->setRegOtherThread(Rd_bits, Rt, tid); - unsigned status_ksu = bits(tc->readMiscReg(MipsISA::Status), - S_KSU_HI, S_KSU_LO); - unsigned tc_status_asid = bits(tc->readMiscReg(MipsISA::TCStatus), - TCS_ASID_HI, TCS_ASID_LO); + StatusReg status = tc->readMiscReg(Status); + TCStatusReg tcStatus = tc->readMiscReg(TCStatus); // Set Run-State to Running - replaceBits(tid_TCStatus, TCSTATUS_RNST_HI, TCSTATUS_RNST_LO, 0); - + tidTCStatus.rnst = 0; // Set Delay-Slot to 0 - replaceBits(tid_TCStatus, TCSTATUS_TDS, 0); - + tidTCStatus.tds = 0; // Set Dirty TC to 1 - replaceBits(tid_TCStatus, TCSTATUS_DT, 1); - + tidTCStatus.dt = 1; // Set Activated to 1 - replaceBits(tid_TCStatus, TCSTATUS_A, 1); - + tidTCStatus.a = 1; // Set status to previous thread's status - replaceBits(tid_TCStatus, TCSTATUS_TKSU_HI, TCSTATUS_TKSU_LO, status_ksu); - + tidTCStatus.tksu = status.ksu; // Set ASID to previous thread's state - replaceBits(tid_TCStatus, TCSTATUS_ASID_HI, TCSTATUS_ASID_LO, tc_status_asid); + tidTCStatus.asid = tcStatus.asid; // Write Status Register - tc->setRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag, - tid_TCStatus, tid); + tc->setRegOtherThread(TCStatus + Ctrl_Base_DepTag, + tidTCStatus, tid); // Mark As Successful Fork success = 1; @@ -169,8 +161,9 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt) } if (success == 0) { - unsigned vpe_control = tc->readMiscRegNoEffect(MipsISA::VPEControl); - tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 1)); + VPEControlReg vpeControl = tc->readMiscRegNoEffect(VPEControl); + vpeControl.excpt = 1; + tc->setMiscReg(VPEControl, vpeControl); fault = new ThreadFault(); } } @@ -181,68 +174,54 @@ int yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask) { if (src_reg == 0) { - unsigned mvpconf0 = tc->readMiscRegNoEffect(MVPConf0); - ThreadID num_threads = bits(mvpconf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1; + MVPConf0Reg mvpConf0 = tc->readMiscRegNoEffect(MVPConf0); + ThreadID num_threads = mvpConf0.ptc + 1; int ok = 0; // Get Current VPE & TC numbers from calling thread - unsigned tcbind = tc->readMiscRegNoEffect(TCBind); - unsigned cur_vpe = bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO); - unsigned cur_tc = bits(tcbind, TCB_CUR_TC_HI, TCB_CUR_TC_LO); + TCBindReg tcBind = tc->readMiscRegNoEffect(TCBind); for (ThreadID tid = 0; tid < num_threads; tid++) { - unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag, - tid); - unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag, - tid); - unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag, - tid); - - unsigned tid_vpe = bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO); - unsigned tid_tc = bits(tid_TCBind, TCB_CUR_TC_HI, TCB_CUR_TC_LO); - unsigned tid_tcstatus_da = bits(tid_TCStatus, TCS_DA); - unsigned tid_tcstatus_a = bits(tid_TCStatus, TCS_A); - unsigned tid_tchalt_h = bits(tid_TCHalt, TCH_H); - - if (tid_vpe == cur_vpe && - tid_tc == cur_tc && - tid_tcstatus_da == 1 && - tid_tchalt_h == 0 && - tid_tcstatus_a == 1) { + TCStatusReg tidTCStatus = + tc->readRegOtherThread(TCStatus + Ctrl_Base_DepTag, tid); + TCHaltReg tidTCHalt = + tc->readRegOtherThread(TCHalt + Ctrl_Base_DepTag, tid); + TCBindReg tidTCBind = + tc->readRegOtherThread(TCBind + Ctrl_Base_DepTag, tid); + + if (tidTCBind.curVPE == tcBind.curVPE && + tidTCBind.curTC == tcBind.curTC && + tidTCStatus.da == 1 && + tidTCHalt.h == 0 && + tidTCStatus.a == 1) { ok = 1; } } if (ok == 1) { - unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus); - tc->setMiscReg(TCStatus, insertBits(tcstatus, TCS_A, TCS_A, 0)); - warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->threadId()); + TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus); + tcStatus.a = 0; + tc->setMiscReg(TCStatus, tcStatus); + warn("%i: Deactivating Hardware Thread Context #%i", + curTick, tc->threadId()); } } else if (src_reg > 0) { if (src_reg && !yield_mask != 0) { - unsigned vpe_control = tc->readMiscReg(VPEControl); - tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 2)); + VPEControlReg vpeControl = tc->readMiscReg(VPEControl); + vpeControl.excpt = 2; + tc->setMiscReg(VPEControl, vpeControl); fault = new ThreadFault(); } else { - //tc->setThreadRescheduleCondition(src_reg & yield_mask); } } else if (src_reg != -2) { - unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus); - unsigned vpe_control = tc->readMiscRegNoEffect(VPEControl); - unsigned tcstatus_dt = bits(tcstatus, TCS_DT); - unsigned vpe_control_ysi = bits(vpe_control, VPEC_YSI); + TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus); + VPEControlReg vpeControl = tc->readMiscRegNoEffect(VPEControl); - if (vpe_control_ysi == 1 && tcstatus_dt == 1 ) { - tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 4)); + if (vpeControl.ysi == 1 && tcStatus.dt == 1 ) { + vpeControl.excpt = 4; fault = new ThreadFault(); } else { - //tc->ScheduleOtherThreads(); - //std::cerr << "T" << tc->threadId() << "YIELD: Schedule Other Threads.\n" << std::endl; - //tc->suspend(); - // Save last known PC in TCRestart - // @TODO: Needs to check if this is a branch and if so, take previous instruction - //tc->setMiscRegWithEffect(TCRestart, tc->readNextPC()); } } @@ -258,17 +237,12 @@ updateStatusView(TC *tc) { // TCStatus' register view must be the same as // Status register view for CU, MX, KSU bits - MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus); - MiscReg status = tc->readMiscRegNoEffect(Status); - - unsigned cu_bits = bits(tc_status, TCS_TCU_HI, TCS_TCU_LO); - replaceBits(status, S_CU_HI, S_CU_LO, cu_bits); - - unsigned mx_bits = bits(tc_status, TCS_TMX); - replaceBits(status, S_MX, S_MX, mx_bits); + TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus); + StatusReg status = tc->readMiscRegNoEffect(Status); - unsigned ksu_bits = bits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO); - replaceBits(status, S_KSU_HI, S_KSU_LO, ksu_bits); + status.cu = tcStatus.tcu; + status.mx = tcStatus.tmx; + status.ksu = tcStatus.tksu; tc->setMiscRegNoEffect(Status, status); } @@ -281,19 +255,14 @@ updateTCStatusView(TC *tc) { // TCStatus' register view must be the same as // Status register view for CU, MX, KSU bits - MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus); - MiscReg status = tc->readMiscRegNoEffect(Status); - - unsigned cu_bits = bits(status, S_CU_HI, S_CU_LO); - replaceBits(tc_status, TCS_TCU_HI, TCS_TCU_LO, cu_bits); - - unsigned mx_bits = bits(status, S_MX, S_MX); - replaceBits(tc_status, TCS_TMX, mx_bits); + TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus); + StatusReg status = tc->readMiscRegNoEffect(Status); - unsigned ksu_bits = bits(status, S_KSU_HI, S_KSU_LO); - replaceBits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO, ksu_bits); + tcStatus.tcu = status.cu; + tcStatus.tmx = status.mx; + tcStatus.tksu = status.ksu; - tc->setMiscRegNoEffect(TCStatus, tc_status); + tc->setMiscRegNoEffect(TCStatus, tcStatus); } } // namespace MipsISA |