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-rwxr-xr-xsrc/arch/mips/pagetable.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh
index cc4e4a859..cb129fba7 100755
--- a/src/arch/mips/pagetable.hh
+++ b/src/arch/mips/pagetable.hh
@@ -65,7 +65,7 @@ struct PTE
bool V1; // Odd entry Valid Bit
uint8_t C1; // Cache Coherency Bits (3 bits)
- /*
+ /*
* The next few variables are put in as optimizations to reduce
* TLB lookup overheads. For a given Mask, what is the address shift
* amount, and what is the OffsetMask