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-rw-r--r--src/arch/mips/regfile/misc_regfile.hh273
1 files changed, 94 insertions, 179 deletions
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 53ee09512..54b086a8b 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -31,213 +31,128 @@
#ifndef __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__
#define __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__
+#include "arch/mips/isa_traits.hh"
#include "arch/mips/types.hh"
+#include "arch/mips/mt.hh"
+#include "arch/mips/mt_constants.hh"
+#include "base/bitfield.hh"
+#include "cpu/base.hh"
#include "sim/faults.hh"
+#include <queue>
class ThreadContext;
namespace MipsISA
{
- static inline std::string getMiscRegName(RegIndex)
- {
- return "";
- }
-
- //Coprocessor 0 Register Names
- enum MiscRegTags {
- //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
- //(Register Number-Register Select) Summary of Register
- //------------------------------------------------------
- Index = 0, //Bank 0: 0 - 3
- MVPControl,
- MVPConf0,
- MVPConf1,
-
- Random = 8, //Bank 1: 8 - 15
- VPEControl,
- VPEConf0,
- VPEConf1,
- YQMask,
- VPESchedule,
- VPEScheFBack,
- VPEOpt,
-
- EntryLo0 = 16, //Bank 2: 16 - 23
- TCStatus,
- TCBind,
- TCRestart,
- TCHalt,
- TCContext,
- TCSchedule,
- TCScheFBack,
-
- EntryLo1 = 24, // Bank 3: 24
-
- Context = 32, // Bank 4: 32 - 33
- ContextConfig,
-
- //PageMask = 40, //Bank 5: 40 - 41
- PageGrain = 41,
-
- Wired = 48, //Bank 6: 48 - 55
- SRSConf0,
- SRSConf1,
- SRSConf2,
- SRSConf3,
- SRSConf4,
-
- HWRena = 56, //Bank 7: 56
-
- BadVAddr = 63, //Bank 8: 63
-
- Count = 64, //Bank 9: 64
-
- EntryHi = 72, //Bank 10:72 - 79
-
- Compare = 80, //Bank 10:80 - 87
-
- Status = 88, //Bank 12:88 - 96
- IntCtl = 89,
- SRSCtl = 90,
- SRSMap = 91,
-
- Cause = 97, //97-104
-
- EPC = 105, //105-112
-
- PRId = 113, //113-120,
- EBase = 114,
-
- Config = 121, //Bank 16: 121-128
- Config1 = 122,
- Config2 = 123,
- Config3 = 124,
- Config6 = 127,
- Config7 = 128,
-
-
- LLAddr = 129, //Bank 17: 129-136
-
- WatchLo0 = 137, //Bank 18: 137-144
- WatchLo1 = 138,
- WatchLo2 = 139,
- WatchLo3 = 140,
- WatchLo4 = 141,
- WatchLo5 = 142,
- WatchLo6 = 143,
- WatchLo7 = 144,
-
- WatchHi0 = 145,//Bank 19: 145-152
- WatchHi1 = 146,
- WatchHi2 = 147,
- WatchHi3 = 148,
- WatchHi4 = 149,
- WatchHi5 = 150,
- WatchHi6 = 151,
- WatchHi7 = 152,
-
- XCContext64 = 153, //Bank 20: 153-160
-
- //Bank 21: 161-168
-
- //Bank 22: 169-176
-
- Debug = 177, //Bank 23: 177-184
- TraceControl1 = 178,
- TraceControl2 = 179,
- UserTraceData = 180,
- TraceBPC = 181,
-
- DEPC = 185,//Bank 24: 185-192
-
- PerfCnt0 = 193,//Bank 25: 193 - 200
- PerfCnt1 = 194,
- PerfCnt2 = 195,
- PerfCnt3 = 196,
- PerfCnt4 = 197,
- PerfCnt5 = 198,
- PerfCnt6 = 199,
- PerfCnt7 = 200,
+ class MiscRegFile {
+ public:
+ // Give RegFile object, private access
+ friend class RegFile;
- ErrCtl = 201, //Bank 26: 201 - 208
+ // The MIPS name for this file is CP0 or Coprocessor 0
+ typedef MiscRegFile CP0;
- CacheErr0 = 209, //Bank 27: 209 - 216
- CacheErr1 = 210,
- CacheErr2 = 211,
- CacheErr3 = 212,
+ protected:
+ enum BankType {
+ perProcessor,
+ perThreadContext,
+ perVirtProcessor
+ };
- TagLo0 = 217,//Bank 28: 217 - 224
- DataLo1 = 218,
- TagLo2 = 219,
- DataLo3 = 220,
- TagLo4 = 221,
- DataLo5 = 222,
- TagLo6 = 223,
- DataLo7 = 234,
+ std::vector<std::vector<MiscReg> > miscRegFile;
+ std::vector<BankType> bankType;
- TagHi0 = 233,//Bank 29: 233 - 240
- DataHi1 = 234,
- TagHi2 = 235,
- DataHi3 = 236,
- TagHi4 = 237,
- DataHi5 = 238,
- TagHi6 = 239,
- DataHi7 = 240,
+ BaseCPU *cpu;
+ public:
+ MiscRegFile();
+ MiscRegFile(BaseCPU *cpu);
- ErrorEPC = 249,//Bank 30: 241 - 248
+ void init();
- DESAVE = 257//Bank 31: 249-256
- };
+ void clear(unsigned tid_or_vpn = 0);
- class MiscRegFile {
+ void reset(std::string core_name, unsigned num_threads, unsigned num_vpes);
- protected:
- uint64_t fpcr; // floating point condition codes
- // FPCR is not used in MIPS. Condition
- // codes are kept as part of the FloatRegFile
+ void expandForMultithreading(unsigned num_threads, unsigned num_vpes);
- bool lock_flag; // lock flag for LL/SC
- // use LL reg. in the future
+ void copyMiscRegs(ThreadContext *tc);
- Addr lock_addr; // lock address for LL/SC
- // use LLAddr reg. in the future
+ inline unsigned getVPENum(unsigned tid);
+
+ //////////////////////////////////////////////////////////
+ //
+ // READ/WRITE CP0 STATE
+ //
+ //
+ //////////////////////////////////////////////////////////
+ //@TODO: MIPS MT's register view automatically connects
+ // Status to TCStatus depending on current thread
+ void updateCP0ReadView(int misc_reg, unsigned tid) { }
+ MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0);
+ MiscReg readReg(int misc_reg,
+ ThreadContext *tc, unsigned tid = 0);
+
+ MiscReg filterCP0Write(int misc_reg, MiscReg val) { return val; }
+ void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
+ void setReg(int misc_reg, const MiscReg &val,
+ ThreadContext *tc, unsigned tid = 0);
- MiscReg miscRegFile[NumMiscRegs];
+ //////////////////////////////////////////////////////////
+ //
+ // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
+ // TO SCHEDULE EVENTS
+ //
+ //////////////////////////////////////////////////////////
- public:
- void clear()
- {
- fpcr = 0;
- lock_flag = 0;
- lock_addr = 0;
- }
+ // Flag that is set when CP0 state has been written to.
+ bool cp0Updated;
- void copyMiscRegs(ThreadContext *tc);
+ // Enumerated List of CP0 Event Types
+ enum CP0EventType {
+ UpdateCP0
+ };
- MiscReg readRegNoEffect(int misc_reg)
+ // Declare A CP0Event Class for scheduling
+ class CP0Event : public Event
{
- return miscRegFile[misc_reg];
- }
+ protected:
+ MiscRegFile::CP0 *cp0;
+ BaseCPU *cpu;
+ CP0EventType cp0EventType;
+ Fault fault;
- MiscReg readReg(int misc_reg, ThreadContext *tc)
- {
- return miscRegFile[misc_reg];
- }
+ public:
+ /** Constructs a CP0 event. */
+ CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type);
- void setRegNoEffect(int misc_reg, const MiscReg &val)
- {
- miscRegFile[misc_reg] = val;
- }
+ /** Process this event. */
+ virtual void process();
- void setReg(int misc_reg, const MiscReg &val,
- ThreadContext *tc)
- {
- miscRegFile[misc_reg] = val;
- }
+ /** Returns the description of this event. */
+ const char *description();
- friend class RegFile;
+ /** Schedule This Event */
+ void scheduleEvent(int delay);
+
+ /** Unschedule This Event */
+ void unscheduleEvent();
+ };
+
+ // Schedule a CP0 Update Event
+ void scheduleCP0Update(int delay = 0);
+
+ // If any changes have been made, then check the state for changes
+ // and if necessary alert the CPU
+ void updateCPU();
+
+ // Keep a List of CPU Events that need to be deallocated
+ std::queue<CP0Event*> cp0EventRemoveList;
+
+ static std::string miscRegNames[NumMiscRegs];
};
+
+ inline std::string getMiscRegName(unsigned reg_idx);
} // namespace MipsISA
#endif
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