4 files changed, 5 insertions, 23 deletions
diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index 1537855df..0c0ecc7eb 100644
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -44,11 +44,6 @@ class Checkpoint;
 
 namespace MipsISA
 {
-    static inline std::string getFloatRegName(RegIndex)
-    {
-        return "";
-    }
-
     const uint32_t MIPS32_QNAN = 0x7fbfffff;
     const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
 
diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh
index 0f453a382..c5a6bb345 100644
--- a/src/arch/mips/regfile/int_regfile.hh
+++ b/src/arch/mips/regfile/int_regfile.hh
@@ -42,11 +42,6 @@ class Checkpoint;
 
 namespace MipsISA
 {
-    static inline std::string getIntRegName(RegIndex)
-    {
-        return "";
-    }
-
     enum MiscIntRegNums {
        LO = NumIntArchRegs,
        HI,
diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc
index 08487db90..ea858abf0 100644
--- a/src/arch/mips/regfile/misc_regfile.cc
+++ b/src/arch/mips/regfile/misc_regfile.cc
@@ -437,12 +437,6 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
 
 }
 
-inline std::string
-MipsISA::getMiscRegName(unsigned reg_idx)
-{
-    return MiscRegFile::miscRegNames[reg_idx];
-}
-
 inline unsigned
 MiscRegFile::getVPENum(unsigned tid)
 {
@@ -457,7 +451,7 @@ MiscRegFile::readRegNoEffect(int reg_idx, unsigned tid)
     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
     DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
-            misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),
+            misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
             miscRegFile[misc_reg][reg_sel]);
     return miscRegFile[misc_reg][reg_sel];
 }
@@ -474,7 +468,7 @@ MiscRegFile::readReg(int reg_idx,
         ? tid : getVPENum(tid);
     DPRINTF(MipsPRA,
             "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
-            misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),
+            misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
             miscRegFile[misc_reg][reg_sel]);
 
 
@@ -494,7 +488,7 @@ MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, unsigned tid)
     DPRINTF(MipsPRA,
             "[tid:%i]: Setting (direct set) CP0 Register:%u "
             "Select:%u (%s) to %#x.\n",
-            tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
+            tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
 
     miscRegFile[misc_reg][reg_sel] = val;
 }
@@ -507,7 +501,7 @@ MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, unsigned tid)
         ? tid : getVPENum(tid);
     DPRINTF(MipsPRA,
             "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
-            tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
+            tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
     miscRegFile_WriteMask[misc_reg][reg_sel] = val;
 }
 
@@ -527,7 +521,7 @@ MiscRegFile::setReg(int reg_idx, const MiscReg &val,
     DPRINTF(MipsPRA,
             "[tid:%i]: Setting CP0 Register:%u "
             "Select:%u (%s) to %#x, with effect.\n",
-            tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
+            tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
 
     MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
 
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 4bec9a49e..c611d94cc 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -162,8 +162,6 @@ namespace MipsISA
 
         static std::string miscRegNames[NumMiscRegs];
     };
-
-    inline std::string getMiscRegName(unsigned reg_idx);
 } // namespace MipsISA
 
 #endif