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-rw-r--r--src/arch/mips/regfile/float_regfile.cc13
-rw-r--r--src/arch/mips/regfile/float_regfile.hh10
-rw-r--r--src/arch/mips/regfile/misc_regfile.cc27
-rw-r--r--src/arch/mips/regfile/misc_regfile.hh18
-rw-r--r--src/arch/mips/regfile/regfile.cc12
-rw-r--r--src/arch/mips/regfile/regfile.hh12
6 files changed, 47 insertions, 45 deletions
diff --git a/src/arch/mips/regfile/float_regfile.cc b/src/arch/mips/regfile/float_regfile.cc
index 122d7c229..2b32bd3af 100644
--- a/src/arch/mips/regfile/float_regfile.cc
+++ b/src/arch/mips/regfile/float_regfile.cc
@@ -42,7 +42,7 @@ FloatRegFile::clear()
}
double
-FloatRegFile::readReg(int floatReg, int width, unsigned tid)
+FloatRegFile::readReg(int floatReg, int width, ThreadID tid)
{
switch(width)
{
@@ -65,7 +65,7 @@ FloatRegFile::readReg(int floatReg, int width, unsigned tid)
}
FloatRegBits
-FloatRegFile::readRegBits(int floatReg, int width, unsigned tid)
+FloatRegFile::readRegBits(int floatReg, int width, ThreadID tid)
{
if (floatReg < NumFloatArchRegs - 1) {
switch(width)
@@ -88,9 +88,9 @@ FloatRegFile::readRegBits(int floatReg, int width, unsigned tid)
}
Fault
-FloatRegFile::setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid)
+FloatRegFile::setReg(int floatReg, const FloatRegVal &val, int width,
+ ThreadID tid)
{
- using namespace std;
switch(width)
{
case SingleWidth:
@@ -118,10 +118,9 @@ FloatRegFile::setReg(int floatReg, const FloatRegVal &val, int width, unsigned t
}
Fault
-FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid)
+FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width,
+ ThreadID tid)
{
- using namespace std;
-
switch(width)
{
case SingleWidth:
diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index 7a95d0568..afe6701c5 100644
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -88,10 +88,12 @@ namespace MipsISA
static const int regWidth = SingleWidth;
void clear();
- double readReg(int floatReg, int width, unsigned tid = 0);
- FloatRegBits readRegBits(int floatReg, int width, unsigned tid = 0);
- Fault setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid = 0);
- Fault setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid = 0);
+ double readReg(int floatReg, int width, ThreadID tid = 0);
+ FloatRegBits readRegBits(int floatReg, int width, ThreadID tid = 0);
+ Fault setReg(int floatReg, const FloatRegVal &val, int width,
+ ThreadID tid = 0);
+ Fault setRegBits(int floatReg, const FloatRegBits &val, int width,
+ ThreadID tid = 0);
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc
index a00bf166e..aee4fab4d 100644
--- a/src/arch/mips/regfile/misc_regfile.cc
+++ b/src/arch/mips/regfile/misc_regfile.cc
@@ -131,7 +131,7 @@ MiscRegFile::clear(unsigned tid_or_vpn)
}
void
-MiscRegFile::expandForMultithreading(unsigned num_threads, unsigned num_vpes)
+MiscRegFile::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
{
// Initialize all Per-VPE regs
uint32_t per_vpe_regs[] = { VPEControl, VPEConf0, VPEConf1, YQMask,
@@ -180,7 +180,7 @@ int MiscRegFile:: getDataAsid()
}
//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
void
-MiscRegFile::reset(std::string core_name, unsigned num_threads,
+MiscRegFile::reset(std::string core_name, ThreadID num_threads,
unsigned num_vpes, BaseCPU *_cpu)
{
DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
@@ -378,7 +378,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
setRegNoEffect(VPEConf0, vpe_conf0);
// TCBind
- for (int tid = 0; tid < num_threads; tid++) {
+ for (ThreadID tid = 0; tid < num_threads; tid++) {
MiscReg tc_bind = readRegNoEffect(TCBind, tid);
replaceBits(tc_bind, TCB_CUR_TC_HI, TCB_CUR_TC_LO, tid);
setRegNoEffect(TCBind, tc_bind, tid);
@@ -387,7 +387,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
MiscReg tc_halt = readRegNoEffect(TCHalt);
replaceBits(tc_halt, TCH_H, 0);
setRegNoEffect(TCHalt, tc_halt);
- /*for (int tid = 1; tid < num_threads; tid++) {
+ /*for (ThreadID tid = 1; tid < num_threads; tid++) {
// Set TCHalt Halt bit to 1 for all other threads
tc_halt = readRegNoEffect(TCHalt, tid);
replaceBits(tc_halt, TCH_H, 1);
@@ -401,7 +401,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
setRegNoEffect(TCStatus, tc_status);
// Set Dynamically Allocatable bit to 1 for all other threads
- for (int tid = 1; tid < num_threads; tid++) {
+ for (ThreadID tid = 1; tid < num_threads; tid++) {
tc_status = readRegNoEffect(TCStatus, tid);
replaceBits(tc_status, TCSTATUS_DA, 1);
setRegNoEffect(TCStatus, tc_status, tid);
@@ -439,14 +439,14 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
}
inline unsigned
-MiscRegFile::getVPENum(unsigned tid)
+MiscRegFile::getVPENum(ThreadID tid)
{
unsigned tc_bind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid];
return bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
}
MiscReg
-MiscRegFile::readRegNoEffect(int reg_idx, unsigned tid)
+MiscRegFile::readRegNoEffect(int reg_idx, ThreadID tid)
{
int misc_reg = reg_idx - Ctrl_Base_DepTag;
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
@@ -461,8 +461,7 @@ MiscRegFile::readRegNoEffect(int reg_idx, unsigned tid)
// Status to TCStatus depending on current thread
//template <class TC>
MiscReg
-MiscRegFile::readReg(int reg_idx,
- ThreadContext *tc, unsigned tid)
+MiscRegFile::readReg(int reg_idx, ThreadContext *tc, ThreadID tid)
{
int misc_reg = reg_idx - Ctrl_Base_DepTag;
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
@@ -481,7 +480,7 @@ MiscRegFile::readReg(int reg_idx,
}
void
-MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, unsigned tid)
+MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid)
{
int misc_reg = reg_idx - Ctrl_Base_DepTag;
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
@@ -494,7 +493,7 @@ MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, unsigned tid)
miscRegFile[misc_reg][reg_sel] = val;
}
void
-MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, unsigned tid)
+MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid)
{
// return;
int misc_reg = reg_idx - Ctrl_Base_DepTag;
@@ -513,7 +512,7 @@ MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, unsigned tid)
//template <class TC>
void
MiscRegFile::setReg(int reg_idx, const MiscReg &val,
- ThreadContext *tc, unsigned tid)
+ ThreadContext *tc, ThreadID tid)
{
int misc_reg = reg_idx - Ctrl_Base_DepTag;
int reg_sel = (bankType[misc_reg] == perThreadContext)
@@ -575,9 +574,9 @@ MiscRegFile::updateCPU()
//
///////////////////////////////////////////////////////////////////
unsigned mvp_conf0 = readRegNoEffect(MVPConf0);
- unsigned num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
+ ThreadID num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
- for (int tid = 0; tid < num_threads; tid++) {
+ for (ThreadID tid = 0; tid < num_threads; tid++) {
MiscReg tc_status = readRegNoEffect(TCStatus, tid);
MiscReg tc_halt = readRegNoEffect(TCHalt, tid);
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 0daf8f718..633ea7efb 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -75,12 +75,12 @@ namespace MipsISA
void clear(unsigned tid_or_vpn = 0);
- void reset(std::string core_name, unsigned num_threads,
+ void reset(std::string core_name, ThreadID num_threads,
unsigned num_vpes, BaseCPU *_cpu);
- void expandForMultithreading(unsigned num_threads, unsigned num_vpes);
+ void expandForMultithreading(ThreadID num_threads, unsigned num_vpes);
- inline unsigned getVPENum(unsigned tid);
+ unsigned getVPENum(ThreadID tid);
//////////////////////////////////////////////////////////
//
@@ -90,21 +90,21 @@ namespace MipsISA
//////////////////////////////////////////////////////////
//@TODO: MIPS MT's register view automatically connects
// Status to TCStatus depending on current thread
- void updateCP0ReadView(int misc_reg, unsigned tid) { }
- MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0);
+ void updateCP0ReadView(int misc_reg, ThreadID tid) { }
+ MiscReg readRegNoEffect(int misc_reg, ThreadID tid = 0);
//template <class TC>
MiscReg readReg(int misc_reg,
- ThreadContext *tc, unsigned tid = 0);
+ ThreadContext *tc, ThreadID tid = 0);
MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
- void setRegMask(int misc_reg, const MiscReg &val, unsigned tid = 0);
+ void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0);
void setRegNoEffect(int misc_reg, const MiscReg &val,
- unsigned tid = 0);
+ ThreadID tid = 0);
//template <class TC>
void setReg(int misc_reg, const MiscReg &val,
- ThreadContext *tc, unsigned tid = 0);
+ ThreadContext *tc, ThreadID tid = 0);
int getInstAsid();
int getDataAsid();
diff --git a/src/arch/mips/regfile/regfile.cc b/src/arch/mips/regfile/regfile.cc
index a1c8eab6a..975fad963 100644
--- a/src/arch/mips/regfile/regfile.cc
+++ b/src/arch/mips/regfile/regfile.cc
@@ -46,7 +46,8 @@ RegFile::clear()
}
void
-RegFile::reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu)
+RegFile::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes,
+ BaseCPU *_cpu)
{
bzero(&intRegFile, sizeof(intRegFile));
bzero(&floatRegFile, sizeof(floatRegFile));
@@ -66,27 +67,26 @@ RegFile::setIntReg(int intReg, const IntReg &val)
}
MiscReg
-RegFile::readMiscRegNoEffect(int miscReg, unsigned tid)
+RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid)
{
return miscRegFile.readRegNoEffect(miscReg, tid);
}
MiscReg
-RegFile::readMiscReg(int miscReg, ThreadContext *tc,
- unsigned tid)
+RegFile::readMiscReg(int miscReg, ThreadContext *tc, ThreadID tid)
{
return miscRegFile.readReg(miscReg, tc, tid);
}
void
-RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid)
+RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, ThreadID tid)
{
miscRegFile.setRegNoEffect(miscReg, val, tid);
}
void
RegFile::setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext * tc, unsigned tid)
+ ThreadContext *tc, ThreadID tid)
{
miscRegFile.setReg(miscReg, val, tc, tid);
}
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index ebf793396..91951b078 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -61,19 +61,21 @@ namespace MipsISA
public:
void clear();
- void reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu);
+ void reset(std::string core_name, ThreadID num_threads,
+ unsigned num_vpes, BaseCPU *_cpu);
MiscRegFile *getMiscRegFilePtr();
IntReg readIntReg(int intReg);
Fault setIntReg(int intReg, const IntReg &val);
- MiscReg readMiscRegNoEffect(int miscReg, unsigned tid = 0);
+ MiscReg readMiscRegNoEffect(int miscReg, ThreadID tid = 0);
MiscReg readMiscReg(int miscReg, ThreadContext *tc,
- unsigned tid = 0);
- void setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid = 0);
+ ThreadID tid = 0);
+ void setMiscRegNoEffect(int miscReg, const MiscReg &val,
+ ThreadID tid = 0);
void setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext * tc, unsigned tid = 0);
+ ThreadContext *tc, ThreadID tid = 0);
FloatRegVal readFloatReg(int floatReg);
FloatRegVal readFloatReg(int floatReg, int width);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 17:15:33 +0000