4 files changed, 9 insertions, 44 deletions

diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index e260f681c..61efbb416 100644
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -100,7 +100,7 @@ namespace MipsISA
             }
         }
 
-        Fault setReg(int floatReg, const FloatReg &val, int width)
+        Fault setReg(int floatReg, const FloatRegVal &val, int width)
         {
             using namespace std;
             switch(width)
diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh
index dc82a3c26..5add1b7be 100644
--- a/src/arch/mips/regfile/int_regfile.hh
+++ b/src/arch/mips/regfile/int_regfile.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -65,11 +65,6 @@ namespace MipsISA
 
     };
 
-    enum MiscIntRegNums {
-       HI = NumIntArchRegs,
-       LO
-    };
-
 } // namespace MipsISA
 
 #endif
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index f8aeab8cb..87961f97e 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -45,18 +45,12 @@ namespace MipsISA
 
       protected:
         uint64_t	fpcr;		// floating point condition codes
-        uint64_t	uniq;		// process-unique register
         bool		lock_flag;	// lock flag for LL/SC
         Addr		lock_addr;	// lock address for LL/SC
 
         MiscReg miscRegFile[NumMiscRegs];
 
       public:
-        //These functions should be removed once the simplescalar cpu model
-        //has been replaced.
-        int getInstAsid();
-        int getDataAsid();
-
         void copyMiscRegs(ThreadContext *tc);
 
         MiscReg readReg(int misc_reg)
@@ -80,17 +74,6 @@ namespace MipsISA
             miscRegFile[misc_reg] = val; return NoFault;
         }
 
-#if FULL_SYSTEM
-        void clearIprs() { }
-
-      protected:
-        InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
-
-      private:
-        MiscReg readIpr(int idx, Fault &fault, ThreadContext *tc) { }
-
-        Fault setIpr(int idx, uint64_t val, ThreadContext *tc) { }
-#endif
         friend class RegFile;
     };
 } // namespace MipsISA
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index af61e62cd..a68120299 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -81,12 +81,12 @@ namespace MipsISA
             return miscRegFile.setRegWithEffect(miscReg, val, tc);
         }
 
-        FloatReg readFloatReg(int floatReg)
+        FloatRegVal readFloatReg(int floatReg)
         {
             return floatRegFile.readReg(floatReg,SingleWidth);
         }
 
-        FloatReg readFloatReg(int floatReg, int width)
+        FloatRegVal readFloatReg(int floatReg, int width)
         {
             return floatRegFile.readReg(floatReg,width);
         }
@@ -101,12 +101,12 @@ namespace MipsISA
             return floatRegFile.readRegBits(floatReg,width);
         }
 
-        Fault setFloatReg(int floatReg, const FloatReg &val)
+        Fault setFloatReg(int floatReg, const FloatRegVal &val)
         {
             return floatRegFile.setReg(floatReg, val, SingleWidth);
         }
 
-        Fault setFloatReg(int floatReg, const FloatReg &val, int width)
+        Fault setFloatReg(int floatReg, const FloatRegVal &val, int width)
         {
             return floatRegFile.setReg(floatReg, val, width);
         }
@@ -168,16 +168,6 @@ namespace MipsISA
             nnpc = val;
         }
 
-
-#if FULL_SYSTEM
-        IntReg palregs[NumIntRegs];	// PAL shadow registers
-        InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
-        int intrflag;			// interrupt flag
-        bool pal_shadow;		// using pal_shadow registers
-        inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
-        inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
-#endif // FULL_SYSTEM
-
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
 
@@ -193,9 +183,6 @@ namespace MipsISA
 
     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 
-#if FULL_SYSTEM
-    void copyIprs(ThreadContext *src, ThreadContext *dest);
-#endif
 } // namespace MipsISA
 
 #endif