summaryrefslogtreecommitdiff
path: root/src/arch/mips/regfile
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/mips/regfile')
-rw-r--r--src/arch/mips/regfile/float_regfile.cc152
-rw-r--r--src/arch/mips/regfile/float_regfile.hh101
-rw-r--r--src/arch/mips/regfile/int_regfile.cc56
-rw-r--r--src/arch/mips/regfile/int_regfile.hh26
-rwxr-xr-xsrc/arch/mips/regfile/misc_regfile.cc275
-rw-r--r--src/arch/mips/regfile/misc_regfile.hh25
-rw-r--r--src/arch/mips/regfile/regfile.cc171
-rw-r--r--src/arch/mips/regfile/regfile.hh165
8 files changed, 680 insertions, 291 deletions
diff --git a/src/arch/mips/regfile/float_regfile.cc b/src/arch/mips/regfile/float_regfile.cc
new file mode 100644
index 000000000..122d7c229
--- /dev/null
+++ b/src/arch/mips/regfile/float_regfile.cc
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Korey Sewell
+ */
+
+#include "arch/mips/regfile/float_regfile.hh"
+#include "sim/serialize.hh"
+
+using namespace MipsISA;
+using namespace std;
+
+void
+FloatRegFile::clear()
+{
+ bzero(&regs, sizeof(regs));
+}
+
+double
+FloatRegFile::readReg(int floatReg, int width, unsigned tid)
+{
+ switch(width)
+ {
+ case SingleWidth:
+ {
+ void *float_ptr = &regs[floatReg];
+ return *(float *) float_ptr;
+ }
+
+ case DoubleWidth:
+ {
+ uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
+ void *double_ptr = &double_val;
+ return *(double *) double_ptr;
+ }
+
+ default:
+ panic("Attempted to read a %d bit floating point register!", width);
+ }
+}
+
+FloatRegBits
+FloatRegFile::readRegBits(int floatReg, int width, unsigned tid)
+{
+ if (floatReg < NumFloatArchRegs - 1) {
+ switch(width)
+ {
+ case SingleWidth:
+ return regs[floatReg];
+
+ case DoubleWidth:
+ return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
+
+ default:
+ panic("Attempted to read a %d bit floating point register!", width);
+ }
+ } else {
+ if (width > SingleWidth)
+ assert("Control Regs are only 32 bits wide");
+
+ return regs[floatReg];
+ }
+}
+
+Fault
+FloatRegFile::setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid)
+{
+ using namespace std;
+ switch(width)
+ {
+ case SingleWidth:
+ {
+ float temp = val;
+ void *float_ptr = &temp;
+ regs[floatReg] = *(FloatReg32 *) float_ptr;
+ break;
+ }
+
+ case DoubleWidth:
+ {
+ const void *double_ptr = &val;
+ FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
+ regs[floatReg + 1] = bits(temp_double, 63, 32);
+ regs[floatReg] = bits(temp_double, 31, 0);
+ break;
+ }
+
+ default:
+ panic("Attempted to read a %d bit floating point register!", width);
+ }
+
+ return NoFault;
+}
+
+Fault
+FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid)
+{
+ using namespace std;
+
+ switch(width)
+ {
+ case SingleWidth:
+ regs[floatReg] = val;
+ break;
+
+ case DoubleWidth:
+ regs[floatReg + 1] = bits(val, 63, 32);
+ regs[floatReg] = bits(val, 31, 0);
+ break;
+
+ default:
+ panic("Attempted to read a %d bit floating point register!", width);
+ }
+ return NoFault;
+}
+
+void
+FloatRegFile::serialize(std::ostream &os)
+{
+ SERIALIZE_ARRAY(regs, NumFloatRegs);
+}
+
+void
+FloatRegFile::unserialize(Checkpoint *cp, const std::string &section)
+{
+ UNSERIALIZE_ARRAY(regs, NumFloatRegs);
+}
diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index 21c16c238..1c869cc4e 100644
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -88,104 +88,13 @@ namespace MipsISA
public:
- void clear() { bzero(&regs, sizeof(regs)); }
-
- double readReg(int floatReg, int width, unsigned tid = 0)
- {
- switch(width)
- {
- case SingleWidth:
- {
- void *float_ptr = &regs[floatReg];
- return *(float *) float_ptr;
- }
-
- case DoubleWidth:
- {
- uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
- void *double_ptr = &double_val;
- return *(double *) double_ptr;
- }
-
- default:
- panic("Attempted to read a %d bit floating point register!", width);
- }
- }
-
- FloatRegBits readRegBits(int floatReg, int width, unsigned tid = 0)
- {
- if (floatReg < NumFloatArchRegs - 1) {
- switch(width)
- {
- case SingleWidth:
- return regs[floatReg];
-
- case DoubleWidth:
- return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
-
- default:
- panic("Attempted to read a %d bit floating point register!", width);
- }
- } else {
- if (width > SingleWidth)
- assert("Control Regs are only 32 bits wide");
-
- return regs[floatReg];
- }
- }
-
- Fault setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid = 0)
- {
- using namespace std;
- switch(width)
- {
- case SingleWidth:
- {
- float temp = val;
- void *float_ptr = &temp;
- regs[floatReg] = *(FloatReg32 *) float_ptr;
- break;
- }
-
- case DoubleWidth:
- {
- const void *double_ptr = &val;
- FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
- regs[floatReg + 1] = bits(temp_double, 63, 32);
- regs[floatReg] = bits(temp_double, 31, 0);
- break;
- }
-
- default:
- panic("Attempted to read a %d bit floating point register!", width);
- }
-
- return NoFault;
- }
-
- Fault setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid = 0)
- {
- using namespace std;
-
- switch(width)
- {
- case SingleWidth:
- regs[floatReg] = val;
- break;
-
- case DoubleWidth:
- regs[floatReg + 1] = bits(val, 63, 32);
- regs[floatReg] = bits(val, 31, 0);
- break;
-
- default:
- panic("Attempted to read a %d bit floating point register!", width);
- }
- return NoFault;
- }
+ void clear();
+ double readReg(int floatReg, int width, unsigned tid = 0);
+ FloatRegBits readRegBits(int floatReg, int width, unsigned tid = 0);
+ Fault setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid = 0);
+ Fault setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid = 0);
void serialize(std::ostream &os);
-
void unserialize(Checkpoint *cp, const std::string &section);
};
diff --git a/src/arch/mips/regfile/int_regfile.cc b/src/arch/mips/regfile/int_regfile.cc
index 70c71fa24..81511b67c 100644
--- a/src/arch/mips/regfile/int_regfile.cc
+++ b/src/arch/mips/regfile/int_regfile.cc
@@ -35,6 +35,61 @@
using namespace MipsISA;
using namespace std;
+
+void
+IntRegFile::clear()
+{
+ bzero(&regs, sizeof(regs));
+ currShadowSet=0;
+}
+
+void
+IntRegFile::setShadowSet(int css)
+{
+ DPRINTF(MipsPRA,"Setting Shadow Set to :%d (%s)\n",css,currShadowSet);
+ currShadowSet = css;
+}
+
+IntReg
+IntRegFile::readReg(int intReg)
+{
+ if(intReg < NumIntRegs)
+ { // Regular GPR Read
+ DPRINTF(MipsPRA,"Reading Reg: %d, CurrShadowSet: %d\n",intReg,currShadowSet);
+ if(intReg >= NumIntArchRegs*NumShadowRegSets){
+ return regs[intReg+NumIntRegs*currShadowSet];
+ }
+ else {
+ return regs[(intReg + NumIntArchRegs*currShadowSet) % NumIntArchRegs];
+ }
+ }
+ else
+ { // Read from shadow GPR .. probably called by RDPGPR
+ return regs[intReg];
+ }
+}
+
+Fault
+IntRegFile::setReg(int intReg, const IntReg &val)
+{
+ if (intReg != ZeroReg) {
+
+ if(intReg < NumIntRegs)
+ {
+ if(intReg >= NumIntArchRegs*NumShadowRegSets){
+ regs[intReg] = val;
+ }
+ else{
+ regs[intReg+NumIntRegs*currShadowSet] = val;
+ }
+ }
+ else{
+ regs[intReg] = val;
+ }
+ }
+ return NoFault;
+}
+
void
IntRegFile::serialize(std::ostream &os)
{
@@ -46,3 +101,4 @@ IntRegFile::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_ARRAY(regs, NumIntRegs);
}
+
diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh
index 2a034ad8d..bdce6bccf 100644
--- a/src/arch/mips/regfile/int_regfile.hh
+++ b/src/arch/mips/regfile/int_regfile.hh
@@ -34,10 +34,10 @@
#include "arch/mips/types.hh"
#include "arch/mips/isa_traits.hh"
#include "base/misc.hh"
+#include "base/trace.hh"
#include "sim/faults.hh"
class Checkpoint;
-class ThreadContext;
namespace MipsISA
{
@@ -47,7 +47,7 @@ namespace MipsISA
}
enum MiscIntRegNums {
- LO = NumIntArchRegs,
+ LO = NumIntArchRegs*NumShadowRegSets,
HI,
DSPACX0,
DSPLo1,
@@ -68,26 +68,14 @@ namespace MipsISA
{
protected:
IntReg regs[NumIntRegs];
-
+ int currShadowSet;
public:
- void clear() { bzero(&regs, sizeof(regs)); }
-
- IntReg readReg(int intReg)
- {
- return regs[intReg];
- }
-
- Fault setReg(int intReg, const IntReg &val)
- {
- if (intReg != ZeroReg) {
- regs[intReg] = val;
- }
-
- return NoFault;
- }
+ void clear();
+ void setShadowSet(int css);
+ IntReg readReg(int intReg);
+ Fault setReg(int intReg, const IntReg &val);
void serialize(std::ostream &os);
-
void unserialize(Checkpoint *cp, const std::string &section);
};
diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc
index 82f284ec4..ae8b7a43c 100755
--- a/src/arch/mips/regfile/misc_regfile.cc
+++ b/src/arch/mips/regfile/misc_regfile.cc
@@ -26,18 +26,18 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Korey Sewell
+ * Jaidev Patwardhan
*/
#include "base/bitfield.hh"
-#include "arch/mips/faults.hh"
-#include "arch/mips/mt.hh"
-#include "arch/mips/mt_constants.hh"
#include "arch/mips/regfile/misc_regfile.hh"
+#include "arch/mips/mt_constants.hh"
+#include "arch/mips/pra_constants.hh"
-#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-//#include "cpu/mixie/cpu.hh"
+#include "cpu/base.hh"
+#include "cpu/exetrace.hh"
using namespace std;
@@ -99,6 +99,11 @@ MiscRegFile::init()
bankType[i] = perProcessor;
}
+ miscRegFile_WriteMask.resize(NumMiscRegs);
+
+ for (int i=0; i < NumMiscRegs; i++) {
+ miscRegFile_WriteMask[i].push_back(0);
+ }
clear(0);
}
@@ -107,6 +112,7 @@ MiscRegFile::clear(unsigned tid_or_vpn)
{
for(int i = 0; i < NumMiscRegs; i++) {
miscRegFile[i][tid_or_vpn] = 0;
+ miscRegFile_WriteMask[i][tid_or_vpn] = (long unsigned int)(-1);
}
}
@@ -147,39 +153,195 @@ MiscRegFile::expandForMultithreading(unsigned num_threads, unsigned num_vpes)
}
}
+int MiscRegFile::getInstAsid()
+{
+ MiscReg Entry_Hi = readRegNoEffect(EntryHi);
+ return bits(Entry_Hi,EntryHi_ASID_HI,EntryHi_ASID_LO);
+}
+int MiscRegFile:: getDataAsid()
+{
+ MiscReg EHi = readRegNoEffect(EntryHi);
+ return bits(EHi,EntryHi_ASID_HI,EntryHi_ASID_LO);
+}
//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
void
MiscRegFile::reset(std::string core_name, unsigned num_threads,
- unsigned num_vpes)
+ unsigned num_vpes, BaseCPU *_cpu)
{
+
DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
num_threads, num_vpes);
-
+ cpu = _cpu;
+ const BaseCPU::Params *p = _cpu->params;
// Do Default CP0 initialization HERE
// Do Initialization for MT cores here (eventually use
// core_name parameter to toggle this initialization)
// ===================================================
+ DPRINTF(MipsPRA, "Initializing CP0 State.... ");
+
+ MiscReg ProcID = readRegNoEffect(PRId);
+ replaceBits(ProcID,PRIdCoOp_HI,PRIdCoOp_LO,p->CP0_PRId_CompanyOptions);
+ replaceBits(ProcID,PRIdCoID_HI,PRIdCoID_LO,p->CP0_PRId_CompanyID);
+ replaceBits(ProcID,PRIdProc_ID_HI,PRIdProc_ID_LO,p->CP0_PRId_ProcessorID);
+ replaceBits(ProcID,PRIdRev_HI,PRIdRev_LO,p->CP0_PRId_Revision);
+ setRegNoEffect(PRId,ProcID);
+ // Now, create Write Mask for ProcID register
+ MiscReg ProcID_Mask = 0; // Read-Only register
+ replaceBits(ProcID_Mask,0,32,0);
+ setRegMask(PRId,ProcID_Mask);
+
// Config
MiscReg cfg = readRegNoEffect(Config);
- replaceBits(cfg, CFG_M, 1);
+ replaceBits(cfg, Config_BE_HI, Config_BE_LO, p->CP0_Config_BE);
+ replaceBits(cfg, Config_AT_HI, Config_AT_LO, p->CP0_Config_AT);
+ replaceBits(cfg, Config_AR_HI, Config_AR_LO, p->CP0_Config_AR);
+ replaceBits(cfg, Config_MT_HI, Config_MT_LO, p->CP0_Config_MT);
+ replaceBits(cfg, Config_VI_HI, Config_VI_LO, p->CP0_Config_VI);
+ replaceBits(cfg, Config_M, 1);
setRegNoEffect(Config, cfg);
+ // Now, create Write Mask for Config register
+ MiscReg cfg_Mask = 0x7FFF0007;
+ replaceBits(cfg_Mask,0,32,0);
+ setRegMask(Config,cfg_Mask);
// Config1
MiscReg cfg1 = readRegNoEffect(Config1);
- replaceBits(cfg1, CFG1_M, 1);
+ replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO, p->CP0_Config1_MMU);
+ replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, p->CP0_Config1_IS);
+ replaceBits(cfg1, Config1_IL_HI, Config1_IL_LO, p->CP0_Config1_IL);
+ replaceBits(cfg1, Config1_IA_HI, Config1_IA_LO, p->CP0_Config1_IA);
+ replaceBits(cfg1, Config1_DS_HI, Config1_DS_LO, p->CP0_Config1_DS);
+ replaceBits(cfg1, Config1_DL_HI, Config1_DL_LO, p->CP0_Config1_DL);
+ replaceBits(cfg1, Config1_DA_HI, Config1_DA_LO, p->CP0_Config1_DA);
+ replaceBits(cfg1, Config1_FP_HI, Config1_FP_LO, p->CP0_Config1_FP);
+ replaceBits(cfg1, Config1_EP_HI, Config1_EP_LO, p->CP0_Config1_EP);
+ replaceBits(cfg1, Config1_WR_HI, Config1_WR_LO, p->CP0_Config1_WR);
+ replaceBits(cfg1, Config1_MD_HI, Config1_MD_LO, p->CP0_Config1_MD);
+ replaceBits(cfg1, Config1_C2_HI, Config1_C2_LO, p->CP0_Config1_C2);
+ replaceBits(cfg1, Config1_PC_HI, Config1_PC_LO, p->CP0_Config1_PC);
+ replaceBits(cfg1, Config1_M, p->CP0_Config1_M);
setRegNoEffect(Config1, cfg1);
+ // Now, create Write Mask for Config register
+ MiscReg cfg1_Mask = 0; // Read Only Register
+ replaceBits(cfg1_Mask,0,32,0);
+ setRegMask(Config1,cfg1_Mask);
// Config2
MiscReg cfg2 = readRegNoEffect(Config2);
- replaceBits(cfg2, CFG2_M, 1);
+ replaceBits(cfg2, Config2_TU_HI, Config2_TU_LO, p->CP0_Config2_TU);
+ replaceBits(cfg2, Config2_TS_HI, Config2_TS_LO, p->CP0_Config2_TS);
+ replaceBits(cfg2, Config2_TL_HI, Config2_TL_LO, p->CP0_Config2_TL);
+ replaceBits(cfg2, Config2_TA_HI, Config2_TA_LO, p->CP0_Config2_TA);
+ replaceBits(cfg2, Config2_SU_HI, Config2_SU_LO, p->CP0_Config2_SU);
+ replaceBits(cfg2, Config2_SS_HI, Config2_SS_LO, p->CP0_Config2_SS);
+ replaceBits(cfg2, Config2_SL_HI, Config2_SL_LO, p->CP0_Config2_SL);
+ replaceBits(cfg2, Config2_SA_HI, Config2_SA_LO, p->CP0_Config2_SA);
+ replaceBits(cfg2, Config2_M, p->CP0_Config2_M);
setRegNoEffect(Config2, cfg2);
+ // Now, create Write Mask for Config register
+ MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
+ replaceBits(cfg2_Mask,0,32,0);
+ setRegMask(Config2,cfg2_Mask);
// Config3
MiscReg cfg3 = readRegNoEffect(Config3);
- replaceBits(cfg3, CFG3_MT, 1);
+ replaceBits(cfg3, Config3_DSPP_HI, Config3_DSPP_LO, p->CP0_Config3_DSPP);
+ replaceBits(cfg3, Config3_LPA_HI, Config3_LPA_LO, p->CP0_Config3_LPA);
+ replaceBits(cfg3, Config3_VEIC_HI, Config3_VEIC_LO, p->CP0_Config3_VEIC);
+ replaceBits(cfg3, Config3_VINT_HI, Config3_VINT_LO, p->CP0_Config3_VInt);
+ replaceBits(cfg3, Config3_SP_HI, Config3_SP_LO, p->CP0_Config3_SP);
+ replaceBits(cfg3, Config3_MT_HI, Config3_MT_LO, p->CP0_Config3_MT);
+ replaceBits(cfg3, Config3_SM_HI, Config3_SM_LO, p->CP0_Config3_SM);
+ replaceBits(cfg3, Config3_TL_HI, Config3_TL_LO, p->CP0_Config3_TL);
setRegNoEffect(Config3, cfg3);
+ // Now, create Write Mask for Config register
+ MiscReg cfg3_Mask = 0; // Read Only Register
+ replaceBits(cfg3_Mask,0,32,0);
+ setRegMask(Config3,cfg3_Mask);
+
+ // EBase - CPUNum
+ MiscReg EB = readRegNoEffect(EBase);
+ replaceBits(EB, EBase_CPUNum_HI, EBase_CPUNum_LO, p->CP0_EBase_CPUNum);
+ replaceBits(EB, 31, 31, 1);
+ setRegNoEffect(EBase, EB);
+ // Now, create Write Mask for Config register
+ MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
+ // entire register is read only
+ replaceBits(EB_Mask,0,32,0);
+ setRegMask(EBase,EB_Mask);
+
+ // SRS Control - HSS (Highest Shadow Set)
+ MiscReg SC = readRegNoEffect(SRSCtl);
+ replaceBits(SC, SRSCtl_HSS_HI,SRSCtl_HSS_LO,p->CP0_SrsCtl_HSS);
+ setRegNoEffect(SRSCtl, SC);
+ // Now, create Write Mask for the SRS Ctl register
+ MiscReg SC_Mask = 0x0000F3C0;
+ replaceBits(SC_Mask,0,32,0);
+ setRegMask(SRSCtl,SC_Mask);
+
+ // IntCtl - IPTI, IPPCI
+ MiscReg IC = readRegNoEffect(IntCtl);
+ replaceBits(IC, IntCtl_IPTI_HI,IntCtl_IPTI_LO,p->CP0_IntCtl_IPTI);
+ replaceBits(IC, IntCtl_IPPCI_HI,IntCtl_IPPCI_LO,p->CP0_IntCtl_IPPCI);
+ setRegNoEffect(IntCtl, IC);
+ // Now, create Write Mask for the IntCtl register
+ MiscReg IC_Mask = 0x000003E0;
+ replaceBits(IC_Mask,0,32,0);
+ setRegMask(IntCtl,IC_Mask);
+
+ // Watch Hi - M - FIXME (More than 1 Watch register)
+ MiscReg WHi = readRegNoEffect(WatchHi0);
+ replaceBits(WHi, WatchHi_M, p->CP0_WatchHi_M);
+ setRegNoEffect(WatchHi0, WHi);
+ // Now, create Write Mask for the IntCtl register
+ MiscReg wh_Mask = 0x7FFF0FFF;
+ replaceBits(wh_Mask,0,32,0);
+ setRegMask(WatchHi0,wh_Mask);
+
+ // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
+ MiscReg PCtr = readRegNoEffect(PerfCnt0);
+ replaceBits(PCtr, PerfCntCtl_M, p->CP0_PerfCtr_M);
+ replaceBits(PCtr, PerfCntCtl_W, p->CP0_PerfCtr_W);
+ setRegNoEffect(PerfCnt0, PCtr);
+ // Now, create Write Mask for the IntCtl register
+ MiscReg pc_Mask = 0x00007FF;
+ replaceBits(pc_Mask,0,32,0);
+ setRegMask(PerfCnt0,pc_Mask);
+
+ // Random
+ MiscReg random = readRegNoEffect(CP0_Random);
+ random = 63;
+ setRegNoEffect(CP0_Random, random);
+ // Now, create Write Mask for the IntCtl register
+ MiscReg random_Mask = 0;
+ replaceBits(random_Mask,0,32,0);
+ setRegMask(CP0_Random,random_Mask);
+
+ // PageGrain
+ MiscReg pagegrain = readRegNoEffect(PageGrain);
+ replaceBits(pagegrain,PageGrain_ESP,p->CP0_Config3_SP);
+ setRegNoEffect(PageGrain, pagegrain);
+ // Now, create Write Mask for the IntCtl register
+ MiscReg pg_Mask = 0x10000000;
+ replaceBits(pg_Mask,0,32,0);
+ setRegMask(PageGrain,pg_Mask);
+
+ // Status
+ MiscReg stat = readRegNoEffect(Status);
+ // Only CU0 and IE are modified on a reset - everything else needs to be controlled
+ // on a per CPU model basis
+ // replaceBits(stat, Status_CU0_HI,Status_CU0_LO, 1); // Enable CP0 on reset
+
+ replaceBits(stat, Status_ERL_HI, Status_ERL_LO, 1); // Enable ERL bit on a reset
+ replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1); // Enable BEV bit on a reset
+ setRegNoEffect(Status, stat);
+ // Now, create Write Mask for the Status register
+ MiscReg stat_Mask = 0xFF78FF17;
+ replaceBits(stat_Mask,0,32,0);
+ setRegMask(Status,stat_Mask);
+
// MVPConf0
MiscReg mvp_conf0 = readRegNoEffect(MVPConf0);
@@ -199,7 +361,6 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
replaceBits(tc_bind, TCB_CUR_TC_HI, TCB_CUR_TC_LO, tid);
setRegNoEffect(TCBind, tc_bind, tid);
}
-
// TCHalt
MiscReg tc_halt = readRegNoEffect(TCHalt);
replaceBits(tc_halt, TCH_H, 0);
@@ -218,11 +379,41 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
setRegNoEffect(TCStatus, tc_status);
// Set Dynamically Allocatable bit to 1 for all other threads
- for (int tid = 0; tid < num_threads; tid++) {
+ for (int tid = 1; tid < num_threads; tid++) {
tc_status = readRegNoEffect(TCStatus, tid);
replaceBits(tc_status, TCSTATUS_DA, 1);
setRegNoEffect(TCStatus, tc_status, tid);
}
+
+
+ MiscReg Mask = 0x7FFFFFFF;
+
+ // Now, create Write Mask for the Index register
+ replaceBits(Mask,0,32,0);
+ setRegMask(Index,Mask);
+
+ Mask = 0x3FFFFFFF;
+ replaceBits(Mask,0,32,0);
+ setRegMask(EntryLo0,Mask);
+ setRegMask(EntryLo1,Mask);
+
+ Mask = 0xFF800000;
+ replaceBits(Mask,0,32,0);
+ setRegMask(Context,Mask);
+
+ Mask = 0x1FFFF800;
+ replaceBits(Mask,0,32,0);
+ setRegMask(PageMask,Mask);
+
+ Mask = 0x0;
+ replaceBits(Mask,0,32,0);
+ setRegMask(BadVAddr,Mask);
+ setRegMask(LLAddr,Mask);
+
+ Mask = 0x08C00300;
+ replaceBits(Mask,0,32,0);
+ setRegMask(Cause,Mask);
+
}
inline std::string
@@ -234,30 +425,34 @@ MipsISA::getMiscRegName(unsigned reg_idx)
inline unsigned
MiscRegFile::getVPENum(unsigned tid)
{
- unsigned tc_bind = miscRegFile[TCBind][tid];
+ unsigned tc_bind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid];
return bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
}
MiscReg
-MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid)
+MiscRegFile::readRegNoEffect(int reg_idx, unsigned tid)
{
+ int misc_reg = reg_idx - Ctrl_Base_DepTag;
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
-
+ DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
+ misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),miscRegFile[misc_reg][reg_sel]);
return miscRegFile[misc_reg][reg_sel];
}
//@TODO: MIPS MT's register view automatically connects
// Status to TCStatus depending on current thread
+//template <class TC>
MiscReg
-MiscRegFile::readReg(int misc_reg,
+MiscRegFile::readReg(int reg_idx,
ThreadContext *tc, unsigned tid)
{
- DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) with effect.\n",
- misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg));
-
+ int misc_reg = reg_idx - Ctrl_Base_DepTag;
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
+ DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
+ misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),miscRegFile[misc_reg][reg_sel]);
+
switch (misc_reg)
{
@@ -267,35 +462,61 @@ MiscRegFile::readReg(int misc_reg,
}
void
-MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
+MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, unsigned tid)
{
+ int misc_reg = reg_idx - Ctrl_Base_DepTag;
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
+ DPRINTF(MipsPRA, "[tid:%i]: Setting (direct set) CP0 Register:%u Select:%u (%s) to %#x.\n",
+ tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
miscRegFile[misc_reg][reg_sel] = val;
}
+void
+MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, unsigned tid)
+{
+ // return;
+ int misc_reg = reg_idx - Ctrl_Base_DepTag;
+ unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
+ ? tid : getVPENum(tid);
+ DPRINTF(MipsPRA,"[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
+ miscRegFile_WriteMask[misc_reg][reg_sel] = val;
+}
// PROGRAMMER'S NOTES:
// (1) Some CP0 Registers have fields that cannot
// be overwritten. Make sure to handle those particular registers
// with care!
+//template <class TC>
void
-MiscRegFile::setReg(int misc_reg, const MiscReg &val,
+MiscRegFile::setReg(int reg_idx, const MiscReg &val,
ThreadContext *tc, unsigned tid)
{
- unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
+ int misc_reg = reg_idx - Ctrl_Base_DepTag;
+ int reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA, "[tid:%i]: Setting CP0 Register:%u Select:%u (%s) to %#x, with effect.\n",
tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
- MiscReg cp0_val = filterCP0Write(misc_reg, val);
+ MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
miscRegFile[misc_reg][reg_sel] = cp0_val;
- scheduleCP0Update();
+ scheduleCP0Update(1);
+}
+/** This method doesn't need to adjust the Control Register Offset since
+ it has already been done in the calling method (setRegWithEffect) */
+MiscReg MiscRegFile::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
+{
+ MiscReg retVal = val;
+ retVal &= miscRegFile_WriteMask[misc_reg][reg_sel]; // Mask off read-only regions
+ MiscReg curVal = miscRegFile[misc_reg][reg_sel];
+ curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]); // Mask off current alue with inverse mask (clear writeable bits)
+ retVal |= curVal; // Combine the two
+ DPRINTF(MipsPRA,"filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, current val: %lx, written val: %x\n",miscRegFile_WriteMask[misc_reg][reg_sel],~miscRegFile_WriteMask[misc_reg][reg_sel],val,miscRegFile[misc_reg][reg_sel],retVal);
+ return retVal;
}
-
void
MiscRegFile::scheduleCP0Update(int delay)
{
@@ -357,7 +578,7 @@ MiscRegFile::CP0Event::process()
const char *
MiscRegFile::CP0Event::description()
{
- return "Coprocessor-0";
+ return "Coprocessor-0 event";
}
void
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 0846378bb..a92215076 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Korey Sewell
+ * Jaidev Patwardhan
*/
#ifndef __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__
@@ -33,11 +34,13 @@
#include "arch/mips/isa_traits.hh"
#include "arch/mips/types.hh"
+#include "arch/mips/mt.hh"
+#include "arch/mips/mt_constants.hh"
+#include "base/bitfield.hh"
#include "sim/eventq.hh"
-#include "sim/faults.hh"
#include <queue>
-class ThreadContext;
+class Params;
class BaseCPU;
namespace MipsISA
@@ -58,6 +61,7 @@ namespace MipsISA
};
std::vector<std::vector<MiscReg> > miscRegFile;
+ std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
std::vector<BankType> bankType;
BaseCPU *cpu;
@@ -70,15 +74,10 @@ namespace MipsISA
void clear(unsigned tid_or_vpn = 0);
- void reset(std::string core_name, unsigned num_threads, unsigned num_vpes);
+ void reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu);
void expandForMultithreading(unsigned num_threads, unsigned num_vpes);
- void copyMiscRegs(ThreadContext *tc)
- {
- panic("Copy Misc. Regs Not Implemented Yet\n");
- }
-
inline unsigned getVPENum(unsigned tid);
//////////////////////////////////////////////////////////
@@ -91,14 +90,22 @@ namespace MipsISA
// Status to TCStatus depending on current thread
void updateCP0ReadView(int misc_reg, unsigned tid) { }
MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0);
+
+ //template <class TC>
MiscReg readReg(int misc_reg,
ThreadContext *tc, unsigned tid = 0);
- MiscReg filterCP0Write(int misc_reg, MiscReg val) { return val; }
+ MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
+ void setRegMask(int misc_reg, const MiscReg &val, unsigned tid = 0);
void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
+
+ //template <class TC>
void setReg(int misc_reg, const MiscReg &val,
ThreadContext *tc, unsigned tid = 0);
+ int getInstAsid();
+ int getDataAsid();
+
//////////////////////////////////////////////////////////
//
// DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
diff --git a/src/arch/mips/regfile/regfile.cc b/src/arch/mips/regfile/regfile.cc
index 2b778e6f8..996c14f14 100644
--- a/src/arch/mips/regfile/regfile.cc
+++ b/src/arch/mips/regfile/regfile.cc
@@ -32,9 +32,166 @@
#include "arch/mips/regfile/regfile.hh"
#include "sim/serialize.hh"
-using namespace MipsISA;
using namespace std;
+namespace MipsISA
+{
+
+void
+RegFile::clear()
+{
+ intRegFile.clear();
+ floatRegFile.clear();
+ miscRegFile.clear();
+}
+
+void
+RegFile::reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu)
+{
+ bzero(&intRegFile, sizeof(intRegFile));
+ bzero(&floatRegFile, sizeof(floatRegFile));
+ miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
+}
+
+IntReg
+RegFile::readIntReg(int intReg)
+{
+ return intRegFile.readReg(intReg);
+}
+
+Fault
+RegFile::setIntReg(int intReg, const IntReg &val)
+{
+ return intRegFile.setReg(intReg, val);
+}
+
+MiscReg
+RegFile::readMiscRegNoEffect(int miscReg, unsigned tid)
+{
+ return miscRegFile.readRegNoEffect(miscReg, tid);
+}
+
+MiscReg
+RegFile::readMiscReg(int miscReg, ThreadContext *tc,
+ unsigned tid)
+{
+ return miscRegFile.readReg(miscReg, tc, tid);
+}
+
+void
+RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid)
+{
+ miscRegFile.setRegNoEffect(miscReg, val, tid);
+}
+
+void
+RegFile::setMiscReg(int miscReg, const MiscReg &val,
+ ThreadContext * tc, unsigned tid)
+{
+ miscRegFile.setReg(miscReg, val, tc, tid);
+}
+
+FloatRegVal
+RegFile::readFloatReg(int floatReg)
+{
+ return floatRegFile.readReg(floatReg,SingleWidth);
+}
+
+FloatRegVal
+RegFile::readFloatReg(int floatReg, int width)
+{
+ return floatRegFile.readReg(floatReg,width);
+}
+
+FloatRegBits
+RegFile::readFloatRegBits(int floatReg)
+{
+ return floatRegFile.readRegBits(floatReg,SingleWidth);
+}
+
+FloatRegBits
+RegFile::readFloatRegBits(int floatReg, int width)
+{
+ return floatRegFile.readRegBits(floatReg,width);
+}
+
+Fault
+RegFile::setFloatReg(int floatReg, const FloatRegVal &val)
+{
+ return floatRegFile.setReg(floatReg, val, SingleWidth);
+}
+
+Fault
+RegFile::setFloatReg(int floatReg, const FloatRegVal &val, int width)
+{
+ return floatRegFile.setReg(floatReg, val, width);
+}
+
+Fault
+RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
+{
+ return floatRegFile.setRegBits(floatReg, val, SingleWidth);
+}
+
+Fault
+RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+{
+ return floatRegFile.setRegBits(floatReg, val, width);
+}
+
+void
+RegFile::setShadowSet(int css){
+ intRegFile.setShadowSet(css);
+}
+
+int
+RegFile::instAsid()
+{
+ return miscRegFile.getInstAsid();
+}
+
+int
+RegFile::dataAsid()
+{
+ return miscRegFile.getDataAsid();
+}
+
+Addr
+RegFile::readPC()
+{
+ return pc;
+}
+
+void
+RegFile::setPC(Addr val)
+{
+ pc = val;
+}
+
+Addr
+RegFile::readNextPC()
+{
+ return npc;
+}
+
+void
+RegFile::setNextPC(Addr val)
+{
+ npc = val;
+}
+
+Addr
+RegFile::readNextNPC()
+{
+ return nnpc;
+}
+
+void
+RegFile::setNextNPC(Addr val)
+{
+ nnpc = val;
+}
+
void
RegFile::serialize(std::ostream &os)
{
@@ -64,14 +221,4 @@ RegFile::unserialize(Checkpoint *cp, const std::string &section)
}
-void
-MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
-{
- panic("Copy Regs Not Implemented Yet\n");
-}
-
-void
-MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
- panic("Copy Misc. Regs Not Implemented Yet\n");
-}
+} // namespace MipsISA
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 4be8d399c..7d100a905 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -32,147 +32,71 @@
#define __ARCH_MIPS_REGFILE_REGFILE_HH__
#include "arch/mips/types.hh"
+#include "arch/mips/isa_traits.hh"
+//#include "arch/mips/mt.hh"
#include "arch/mips/regfile/int_regfile.hh"
#include "arch/mips/regfile/float_regfile.hh"
#include "arch/mips/regfile/misc_regfile.hh"
+//#include "cpu/base.hh"
#include "sim/faults.hh"
class Checkpoint;
-class ThreadContext;
+class BaseCPU;
namespace MipsISA
{
class RegFile {
protected:
+ Addr pc; // program counter
+ Addr npc; // next-cycle program counter
+ Addr nnpc; // next-next-cycle program counter
+ // used to implement branch delay slot
+ // not real register
+
IntRegFile intRegFile; // (signed) integer register file
FloatRegFile floatRegFile; // floating point register file
MiscRegFile miscRegFile; // control register file
public:
- void clear()
- {
- intRegFile.clear();
- floatRegFile.clear();
- miscRegFile.clear();
- }
+ void clear();
+ void reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu);
+ MiscRegFile *getMiscRegFilePtr();
- void reset(std::string core_name, unsigned num_threads, unsigned num_vpes)
- {
- bzero(&intRegFile, sizeof(intRegFile));
- bzero(&floatRegFile, sizeof(floatRegFile));
- miscRegFile.reset(core_name, num_threads, num_vpes);
- }
+ IntReg readIntReg(int intReg);
+ Fault setIntReg(int intReg, const IntReg &val);
- IntReg readIntReg(int intReg)
- {
- return intRegFile.readReg(intReg);
- }
-
- Fault setIntReg(int intReg, const IntReg &val)
- {
- return intRegFile.setReg(intReg, val);
- }
-
- MiscReg readMiscRegNoEffect(int miscReg, unsigned tid = 0)
- {
- return miscRegFile.readRegNoEffect(miscReg, tid);
- }
+ MiscReg readMiscRegNoEffect(int miscReg, unsigned tid = 0);
MiscReg readMiscReg(int miscReg, ThreadContext *tc,
- unsigned tid = 0)
- {
- return miscRegFile.readReg(miscReg, tc, tid);
- }
-
- void setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid = 0)
- {
- miscRegFile.setRegNoEffect(miscReg, val, tid);
- }
-
+ unsigned tid = 0);
+ void setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid = 0);
void setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext * tc, unsigned tid = 0)
- {
- miscRegFile.setReg(miscReg, val, tc, tid);
- }
-
- FloatRegVal readFloatReg(int floatReg)
- {
- return floatRegFile.readReg(floatReg,SingleWidth);
- }
-
- FloatRegVal readFloatReg(int floatReg, int width)
- {
- return floatRegFile.readReg(floatReg,width);
- }
-
- FloatRegBits readFloatRegBits(int floatReg)
- {
- return floatRegFile.readRegBits(floatReg,SingleWidth);
- }
-
- FloatRegBits readFloatRegBits(int floatReg, int width)
- {
- return floatRegFile.readRegBits(floatReg,width);
- }
+ ThreadContext * tc, unsigned tid = 0);
- Fault setFloatReg(int floatReg, const FloatRegVal &val)
- {
- return floatRegFile.setReg(floatReg, val, SingleWidth);
- }
+ FloatRegVal readFloatReg(int floatReg);
+ FloatRegVal readFloatReg(int floatReg, int width);
+ FloatRegBits readFloatRegBits(int floatReg);
+ FloatRegBits readFloatRegBits(int floatReg, int width);
+ Fault setFloatReg(int floatReg, const FloatRegVal &val);
+ Fault setFloatReg(int floatReg, const FloatRegVal &val, int width);
+ Fault setFloatRegBits(int floatReg, const FloatRegBits &val);
+ Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
- Fault setFloatReg(int floatReg, const FloatRegVal &val, int width)
- {
- return floatRegFile.setReg(floatReg, val, width);
- }
- Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
- {
- return floatRegFile.setRegBits(floatReg, val, SingleWidth);
- }
+ void setShadowSet(int css);
- Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
- {
- return floatRegFile.setRegBits(floatReg, val, width);
- }
-
- protected:
-
- Addr pc; // program counter
- Addr npc; // next-cycle program counter
- Addr nnpc; // next-next-cycle program counter
- // used to implement branch delay slot
- // not real register
+ int instAsid();
+ int dataAsid();
public:
- Addr readPC()
- {
- return pc;
- }
+ Addr readPC();
+ void setPC(Addr val);
- void setPC(Addr val)
- {
- pc = val;
- }
-
- Addr readNextPC()
- {
- return npc;
- }
-
- void setNextPC(Addr val)
- {
- npc = val;
- }
-
- Addr readNextNPC()
- {
- return nnpc;
- }
+ Addr readNextPC();
+ void setNextPC(Addr val);
- void setNextNPC(Addr val)
- {
- nnpc = val;
- }
+ Addr readNextNPC();
+ void setNextNPC(Addr val);
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
@@ -180,23 +104,8 @@ namespace MipsISA
void changeContext(RegContextParam param, RegContextVal val)
{
}
- };
- static inline int flattenIntIndex(ThreadContext * tc, int reg)
- {
- return reg;
- }
-
- static inline int flattenFloatIndex(ThreadContext * tc, int reg)
- {
- return reg;
- }
-
- void
- copyRegs(ThreadContext *src, ThreadContext *dest);
-
- void
- copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+ };
} // namespace MipsISA
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 20:15:06 +0000