1 files changed, 70 insertions, 27 deletions

diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 5cf38afbc..7282124a9 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -33,7 +33,7 @@
 
 #ifndef __ARCH_MIPS_UTILITY_HH__
 #define __ARCH_MIPS_UTILITY_HH__
-
+#include "config/full_system.hh"
 #include "arch/mips/types.hh"
 #include "arch/mips/isa_traits.hh"
 #include "base/misc.hh"
@@ -48,13 +48,12 @@ class ThreadContext;
 
 namespace MipsISA {
 
-    inline uint64_t
-    getArgument(ThreadContext *tc, bool fp)
-    {
-        panic("getArgument() not implemented for MIPS\n");
-    }
+    uint64_t getArgument(ThreadContext *tc, int number, bool fp);
 
-    //Floating Point Utility Functions
+    ////////////////////////////////////////////////////////////////////////
+    //
+    // Floating Point Utility Functions
+    //
     uint64_t fpConvert(ConvertType cvt_type, double fp_val);
     double roundFP(double val, int digits);
     double truncFP(double val);
@@ -67,14 +66,21 @@ namespace MipsISA {
     bool isQnan(void *val_ptr, int size);
     bool isSnan(void *val_ptr, int size);
 
-    /**
-     * Function to insure ISA semantics about 0 registers.
-     * @param tc The thread context.
-     */
-    template <class TC>
-    void zeroRegisters(TC *tc);
-
-    void startupCPU(ThreadContext *tc, int cpuId);
+    static inline bool
+    inUserMode(ThreadContext *tc)
+    {
+        MiscReg Stat = tc->readMiscReg(MipsISA::Status);
+        MiscReg Dbg = tc->readMiscReg(MipsISA::Debug);
+
+        if((Stat & 0x10000006) == 0  // EXL, ERL or CU0 set, CP0 accessible
+           && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
+           && (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
+            // Unable to use Status_CU0, etc directly, using bitfields & masks
+            return true;
+        } else {
+            return false;
+        }
+    }
 
     // Instruction address compression hooks
     static inline Addr realPCToFetchPC(const Addr &addr) {
@@ -91,23 +97,60 @@ namespace MipsISA {
         return sizeof(MachInst);
     }
 
+    ////////////////////////////////////////////////////////////////////////
+    //
+    //  Register File Utility Functions
+    //
+    static inline int flattenFloatIndex(ThreadContext * tc, int reg)
+    {
+        return reg;
+    }
+
+    static inline int flattenIntIndex(ThreadContext * tc, int reg)
+    {
+        // Implement Shadow Sets Stuff Here;
+        return reg;
+    }
+
     static inline MachInst makeRegisterCopy(int dest, int src) {
         panic("makeRegisterCopy not implemented");
         return 0;
     }
 
-    static inline ExtMachInst
-    makeExtMI(MachInst inst, ThreadContext * xc) {
-#if FULL_SYSTEM
-        ExtMachInst ext_inst = inst;
-        if (xc->readPC() && 0x1)
-            return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32);
-        else
-            return ext_inst;
-#else
-        return ExtMachInst(inst);
-#endif
-    }
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
+
+    template <class CPU>
+    void zeroRegisters(CPU *cpu);
+
+    ////////////////////////////////////////////////////////////////////////
+    //
+    //  Translation stuff
+    //
+    inline Addr
+    TruncPage(Addr addr)
+    { return addr & ~(PageBytes - 1); }
+
+    inline Addr
+    RoundPage(Addr addr)
+    { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
+
+    ////////////////////////////////////////////////////////////////////////
+    //
+    // CPU Utility
+    //
+    void initCPU(ThreadContext *tc, int cpuId);
+
+    /**
+     * Function to check for and process any interrupts.
+     * @param tc The thread context.
+     */
+    template <class TC>
+    void processInterrupts(TC *tc);
+
+    void startupCPU(ThreadContext *tc, int cpuId);
 };