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-rwxr-xr-xsrc/arch/mips/interrupts.hh4
-rw-r--r--src/arch/mips/tlb.hh4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh
index 3c9165bfa..b5323e4e1 100755
--- a/src/arch/mips/interrupts.hh
+++ b/src/arch/mips/interrupts.hh
@@ -116,13 +116,13 @@ class Interrupts : public SimObject
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
fatal("Serialization of Interrupts Unimplemented for MIPS");
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
fatal("Unserialization of Interrupts Unimplemented for MIPS");
}
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 5a9069e4c..a2f356e1f 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -107,8 +107,8 @@ class TLB : public BaseTLB
static Fault checkCacheability(RequestPtr &req);
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void regStats();