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-rw-r--r--src/arch/mips/isa_traits.hh10
-rw-r--r--src/arch/mips/linux/linux.cc40
-rw-r--r--src/arch/mips/linux/linux.hh40
-rw-r--r--src/arch/mips/regfile/regfile.hh12
-rwxr-xr-xsrc/arch/mips/system.cc6
-rw-r--r--src/arch/mips/tlb.cc32
-rw-r--r--src/arch/mips/tlb.hh8
7 files changed, 74 insertions, 74 deletions
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index fe28ad601..d4d1de479 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -147,11 +147,11 @@ namespace MipsISA
// MIPS modes
enum mode_type
{
- mode_kernel = 0, // kernel
- mode_supervisor = 1, // supervisor
- mode_user = 2, // user mode
+ mode_kernel = 0, // kernel
+ mode_supervisor = 1, // supervisor
+ mode_user = 2, // user mode
mode_debug = 3, // debug mode
- mode_number // number of modes
+ mode_number // number of modes
};
inline mode_type getOperatingMode(MiscReg Stat)
@@ -209,7 +209,7 @@ namespace MipsISA
const int SyscallPseudoReturnReg = ReturnValueReg2;
const int SyscallSuccessReg = ArgumentReg3;
- const int LogVMPageSize = 13; // 8K bytes
+ const int LogVMPageSize = 13; // 8K bytes
const int VMPageSize = (1 << LogVMPageSize);
const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
diff --git a/src/arch/mips/linux/linux.cc b/src/arch/mips/linux/linux.cc
index 4499107d7..8745731dc 100644
--- a/src/arch/mips/linux/linux.cc
+++ b/src/arch/mips/linux/linux.cc
@@ -35,34 +35,34 @@
// open(2) flags translation table
OpenFlagTransTable MipsLinux::openFlagTable[] = {
#ifdef _MSC_VER
- { MipsLinux::TGT_O_RDONLY, _O_RDONLY },
- { MipsLinux::TGT_O_WRONLY, _O_WRONLY },
- { MipsLinux::TGT_O_RDWR, _O_RDWR },
- { MipsLinux::TGT_O_APPEND, _O_APPEND },
- { MipsLinux::TGT_O_CREAT, _O_CREAT },
- { MipsLinux::TGT_O_TRUNC, _O_TRUNC },
- { MipsLinux::TGT_O_EXCL, _O_EXCL },
+ { MipsLinux::TGT_O_RDONLY, _O_RDONLY },
+ { MipsLinux::TGT_O_WRONLY, _O_WRONLY },
+ { MipsLinux::TGT_O_RDWR, _O_RDWR },
+ { MipsLinux::TGT_O_APPEND, _O_APPEND },
+ { MipsLinux::TGT_O_CREAT, _O_CREAT },
+ { MipsLinux::TGT_O_TRUNC, _O_TRUNC },
+ { MipsLinux::TGT_O_EXCL, _O_EXCL },
#ifdef _O_NONBLOCK
- { MipsLinux::TGT_O_NONBLOCK, _O_NONBLOCK },
+ { MipsLinux::TGT_O_NONBLOCK, _O_NONBLOCK },
#endif
#ifdef _O_NOCTTY
- { MipsLinux::TGT_O_NOCTTY, _O_NOCTTY },
+ { MipsLinux::TGT_O_NOCTTY, _O_NOCTTY },
#endif
#ifdef _O_SYNC
- { MipsLinux::TGT_O_SYNC, _O_SYNC },
+ { MipsLinux::TGT_O_SYNC, _O_SYNC },
#endif
#else /* !_MSC_VER */
- { MipsLinux::TGT_O_RDONLY, O_RDONLY },
- { MipsLinux::TGT_O_WRONLY, O_WRONLY },
- { MipsLinux::TGT_O_RDWR, O_RDWR },
- { MipsLinux::TGT_O_APPEND, O_APPEND },
- { MipsLinux::TGT_O_CREAT, O_CREAT },
- { MipsLinux::TGT_O_TRUNC, O_TRUNC },
- { MipsLinux::TGT_O_EXCL, O_EXCL },
- { MipsLinux::TGT_O_NONBLOCK, O_NONBLOCK },
- { MipsLinux::TGT_O_NOCTTY, O_NOCTTY },
+ { MipsLinux::TGT_O_RDONLY, O_RDONLY },
+ { MipsLinux::TGT_O_WRONLY, O_WRONLY },
+ { MipsLinux::TGT_O_RDWR, O_RDWR },
+ { MipsLinux::TGT_O_APPEND, O_APPEND },
+ { MipsLinux::TGT_O_CREAT, O_CREAT },
+ { MipsLinux::TGT_O_TRUNC, O_TRUNC },
+ { MipsLinux::TGT_O_EXCL, O_EXCL },
+ { MipsLinux::TGT_O_NONBLOCK, O_NONBLOCK },
+ { MipsLinux::TGT_O_NOCTTY, O_NOCTTY },
#ifdef O_SYNC
- { MipsLinux::TGT_O_SYNC, O_SYNC },
+ { MipsLinux::TGT_O_SYNC, O_SYNC },
#endif
#endif /* _MSC_VER */
};
diff --git a/src/arch/mips/linux/linux.hh b/src/arch/mips/linux/linux.hh
index fcfaa18ea..0d71a3c58 100644
--- a/src/arch/mips/linux/linux.hh
+++ b/src/arch/mips/linux/linux.hh
@@ -49,21 +49,21 @@ class MipsLinux : public Linux
//@{
/// open(2) flag values.
- static const int TGT_O_RDONLY = 0x00000000; //!< O_RDONLY
- static const int TGT_O_WRONLY = 0x00000001; //!< O_WRONLY
- static const int TGT_O_RDWR = 0x00000002; //!< O_RDWR
- static const int TGT_O_NONBLOCK = 0x00000080; //!< O_NONBLOCK
- static const int TGT_O_APPEND = 0x00000008; //!< O_APPEND
- static const int TGT_O_CREAT = 0x00000100; //!< O_CREAT
- static const int TGT_O_TRUNC = 0x00000200; //!< O_TRUNC
- static const int TGT_O_EXCL = 0x00000400; //!< O_EXCL
- static const int TGT_O_NOCTTY = 0x00000800; //!< O_NOCTTY
- static const int TGT_O_SYNC = 0x00000010; //!< O_SYNC
- static const int TGT_O_DRD = 0x00010000; //!< O_DRD
- static const int TGT_O_DIRECTIO = 0x00020000; //!< O_DIRECTIO
- static const int TGT_O_CACHE = 0x00002000; //!< O_CACHE
- static const int TGT_O_DSYNC = 0x00008000; //!< O_DSYNC
- static const int TGT_O_RSYNC = 0x00040000; //!< O_RSYNC
+ static const int TGT_O_RDONLY = 0x00000000; //!< O_RDONLY
+ static const int TGT_O_WRONLY = 0x00000001; //!< O_WRONLY
+ static const int TGT_O_RDWR = 0x00000002; //!< O_RDWR
+ static const int TGT_O_NONBLOCK = 0x00000080; //!< O_NONBLOCK
+ static const int TGT_O_APPEND = 0x00000008; //!< O_APPEND
+ static const int TGT_O_CREAT = 0x00000100; //!< O_CREAT
+ static const int TGT_O_TRUNC = 0x00000200; //!< O_TRUNC
+ static const int TGT_O_EXCL = 0x00000400; //!< O_EXCL
+ static const int TGT_O_NOCTTY = 0x00000800; //!< O_NOCTTY
+ static const int TGT_O_SYNC = 0x00000010; //!< O_SYNC
+ static const int TGT_O_DRD = 0x00010000; //!< O_DRD
+ static const int TGT_O_DIRECTIO = 0x00020000; //!< O_DIRECTIO
+ static const int TGT_O_CACHE = 0x00002000; //!< O_CACHE
+ static const int TGT_O_DSYNC = 0x00008000; //!< O_DSYNC
+ static const int TGT_O_RSYNC = 0x00040000; //!< O_RSYNC
//@}
/// For mmap().
@@ -72,12 +72,12 @@ class MipsLinux : public Linux
//@{
/// For getsysinfo().
static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name as string
- static const unsigned GSI_CPU_INFO = 59; //!< CPU information
- static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type
+ static const unsigned GSI_CPU_INFO = 59; //!< CPU information
+ static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type
static const unsigned GSI_MAX_CPU = 30; //!< max # cpu's on this machine
- static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system
- static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB
- static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz
+ static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system
+ static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB
+ static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz
//@}
//@{
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 8304b7cda..407d9b50a 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -48,15 +48,15 @@ namespace MipsISA
{
class RegFile {
protected:
- Addr pc; // program counter
- Addr npc; // next-cycle program counter
- Addr nnpc; // next-next-cycle program counter
+ Addr pc; // program counter
+ Addr npc; // next-cycle program counter
+ Addr nnpc; // next-next-cycle program counter
// used to implement branch delay slot
// not real register
- IntRegFile intRegFile; // (signed) integer register file
- FloatRegFile floatRegFile; // floating point register file
- MiscRegFile miscRegFile; // control register file
+ IntRegFile intRegFile; // (signed) integer register file
+ FloatRegFile floatRegFile; // floating point register file
+ MiscRegFile miscRegFile; // control register file
public:
void clear();
diff --git a/src/arch/mips/system.cc b/src/arch/mips/system.cc
index 605acfe32..bf86bb030 100755
--- a/src/arch/mips/system.cc
+++ b/src/arch/mips/system.cc
@@ -134,9 +134,9 @@ MipsSystem::~MipsSystem()
* in the procedure value register (pv aka t12 == r27). This sequence
* looks like the following:
*
- * opcode Ra Rb offset
- * ldah gp,X(pv) 09 29 27 X
- * lda gp,Y(gp) 08 29 29 Y
+ * opcode Ra Rb offset
+ * ldah gp,X(pv) 09 29 27 X
+ * lda gp,Y(gp) 08 29 29 Y
*
* for some constant offsets X and Y. The catch is that the linker
* (or maybe even the compiler, I'm not sure) may recognize that the
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index d78aefab4..7c3b6aed5 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -59,7 +59,7 @@ using namespace MipsISA;
// MIPS TLB
//
-#define MODE2MASK(X) (1 << (X))
+#define MODE2MASK(X) (1 << (X))
TLB::TLB(const Params *p)
: BaseTLB(p), size(p->size), nlu(0)
@@ -91,7 +91,7 @@ TLB::lookup(Addr vpn, uint8_t asn) const
Addr Mask = pte->Mask;
Addr InvMask = ~Mask;
Addr VPN = pte->VPN;
- // warn("Valid: %d - %d\n",pte->V0,pte->V1);
+ // warn("Valid: %d - %d\n",pte->V0,pte->V1);
if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid)))
{ // We have a VPN + ASID Match
retval = pte;
@@ -389,7 +389,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
}
else
{// Ok, this is really a match, set paddr
- // hits++;
+ // hits++;
Addr PAddr;
if(EvenOdd == 0){
PAddr = pte->PFN0;
@@ -406,7 +406,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
}
else
{ // Didn't find any match, return a TLB Refill Exception
- // misses++;
+ // misses++;
ItbRefillFault *Flt=new ItbRefillFault();
/* EntryHi VPN, ASID fields must be set */
Flt->EntryHi_Asid = Asid;
@@ -494,7 +494,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
if(Valid == false)
{//Invalid entry
- // invalids++;
+ // invalids++;
DtbInvalidFault *Flt = new DtbInvalidFault();
/* EntryHi VPN, ASID fields must be set */
Flt->EntryHi_Asid = Asid;
@@ -512,7 +512,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
}
else
{// Ok, this is really a match, set paddr
- // hits++;
+ // hits++;
if(!Dirty)
{
TLBModifiedFault *Flt = new TLBModifiedFault();
@@ -544,7 +544,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
}
else
{ // Didn't find any match, return a TLB Refill Exception
- // misses++;
+ // misses++;
DtbRefillFault *Flt=new DtbRefillFault();
/* EntryHi VPN, ASID fields must be set */
Flt->EntryHi_Asid = Asid;
@@ -577,19 +577,19 @@ ITB::ITB(const Params *p)
// ITB::regStats()
// {
// /* hits - causes failure for some reason
-// .name(name() + ".hits")
-// .desc("ITB hits");
+// .name(name() + ".hits")
+// .desc("ITB hits");
// misses
-// .name(name() + ".misses")
-// .desc("ITB misses");
+// .name(name() + ".misses")
+// .desc("ITB misses");
// acv
-// .name(name() + ".acv")
-// .desc("ITB acv");
+// .name(name() + ".acv")
+// .desc("ITB acv");
// accesses
-// .name(name() + ".accesses")
-// .desc("ITB accesses");
+// .name(name() + ".accesses")
+// .desc("ITB accesses");
-// accesses = hits + misses + invalids; */
+// accesses = hits + misses + invalids; */
// }
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 4333777ff..feb2509c5 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -84,11 +84,11 @@ class TLB : public BaseTLB
{
protected:
typedef std::multimap<Addr, int> PageTable;
- PageTable lookupTable; // Quick lookup into page table
+ PageTable lookupTable; // Quick lookup into page table
- MipsISA::PTE *table; // the Page Table
- int size; // TLB Size
- int nlu; // not last used entry (for replacement)
+ MipsISA::PTE *table; // the Page Table
+ int size; // TLB Size
+ int nlu; // not last used entry (for replacement)
void nextnlu() { if (++nlu >= size) nlu = 0; }
MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 11:00:02 +0000