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-rw-r--r--src/arch/mips/tlb.hh8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index a2f356e1f..af9183192 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -87,7 +87,7 @@ class TLB : public BaseTLB
MipsISA::PTE *getEntry(unsigned) const;
virtual ~TLB();
- void takeOverFrom(BaseTLB *otlb) {}
+ void takeOverFrom(BaseTLB *otlb) override {}
int smallPages;
int getsize() const { return size; }
@@ -95,8 +95,8 @@ class TLB : public BaseTLB
MipsISA::PTE &index(bool advance = true);
void insert(Addr vaddr, MipsISA::PTE &pte);
void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
- void flushAll();
- void demapPage(Addr vaddr, uint64_t asn)
+ void flushAll() override;
+ void demapPage(Addr vaddr, uint64_t asn) override
{
panic("demapPage unimplemented.\n");
}
@@ -110,7 +110,7 @@ class TLB : public BaseTLB
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
- void regStats();
+ void regStats() override;
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,