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-rw-r--r--src/arch/mips/faults.cc22
-rw-r--r--src/arch/mips/faults.hh4
-rw-r--r--src/arch/mips/isa_traits.cc4
-rw-r--r--src/arch/mips/isa_traits.hh10
-rw-r--r--src/arch/mips/linux/process.cc28
-rw-r--r--src/arch/mips/process.cc2
-rw-r--r--src/arch/mips/regfile/float_regfile.hh2
-rw-r--r--src/arch/mips/regfile/int_regfile.hh2
-rw-r--r--src/arch/mips/regfile/misc_regfile.hh12
-rw-r--r--src/arch/mips/regfile/regfile.hh16
-rw-r--r--src/arch/mips/stacktrace.hh22
11 files changed, 62 insertions, 62 deletions
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index fa7275908..810c3fed4 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -29,7 +29,7 @@
*/
#include "arch/mips/faults.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "base/trace.hh"
@@ -102,28 +102,28 @@ FaultStat IntegerOverflowFault::_count;
#if FULL_SYSTEM
-void MipsFault::invoke(ExecContext * xc)
+void MipsFault::invoke(ThreadContext * tc)
{
- FaultBase::invoke(xc);
+ FaultBase::invoke(tc);
countStat()++;
// exception restart address
- if (setRestartAddress() || !xc->inPalMode())
- xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC());
+ if (setRestartAddress() || !tc->inPalMode())
+ tc->setMiscReg(MipsISA::IPR_EXC_ADDR, tc->readPC());
if (skipFaultingInstruction()) {
// traps... skip faulting instruction.
- xc->setMiscReg(MipsISA::IPR_EXC_ADDR,
- xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
+ tc->setMiscReg(MipsISA::IPR_EXC_ADDR,
+ tc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
}
- xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
- xc->setNextPC(xc->readPC() + sizeof(MachInst));
+ tc->setPC(tc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
+ tc->setNextPC(tc->readPC() + sizeof(MachInst));
}
-void ArithmeticFault::invoke(ExecContext * xc)
+void ArithmeticFault::invoke(ThreadContext * tc)
{
- FaultBase::invoke(xc);
+ FaultBase::invoke(tc);
panic("Arithmetic traps are unimplemented!");
}
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 134fa2c4e..d8bf59cc1 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -47,7 +47,7 @@ class MipsFault : public FaultBase
virtual bool setRestartAddress() {return true;}
public:
#if FULL_SYSTEM
- void invoke(ExecContext * xc);
+ void invoke(ThreadContext * tc);
#endif
virtual FaultVect vect() = 0;
virtual FaultStat & countStat() = 0;
@@ -114,7 +114,7 @@ class ArithmeticFault : public MipsFault
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
#if FULL_SYSTEM
- void invoke(ExecContext * xc);
+ void invoke(ThreadContext * tc);
#endif
};
diff --git a/src/arch/mips/isa_traits.cc b/src/arch/mips/isa_traits.cc
index f577a1c94..056c8baff 100644
--- a/src/arch/mips/isa_traits.cc
+++ b/src/arch/mips/isa_traits.cc
@@ -40,7 +40,7 @@ using namespace std;
void
-MipsISA::copyRegs(ExecContext *src, ExecContext *dest)
+MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
{
/*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
@@ -53,7 +53,7 @@ MipsISA::copyRegs(ExecContext *src, ExecContext *dest)
}
void
-MipsISA::MiscRegFile::copyMiscRegs(ExecContext *xc)
+MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
{
/*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index e99bc7395..dc8b6758a 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -48,7 +48,7 @@
class FastCPU;
class FullCPU;
class Checkpoint;
-class ExecContext;
+class ThreadContext;
namespace LittleEndianGuest {};
@@ -131,14 +131,14 @@ namespace MipsISA
/**
* Function to insure ISA semantics about 0 registers.
- * @param xc The execution context.
+ * @param tc The thread context.
*/
- template <class XC>
- void zeroRegisters(XC *xc);
+ template <class TC>
+ void zeroRegisters(TC *tc);
const Addr MaxAddr = (Addr)-1;
- void copyRegs(ExecContext *src, ExecContext *dest);
+ void copyRegs(ThreadContext *src, ThreadContext *dest);
uint64_t fpConvert(double fp_val, ConvertType cvt_type);
double roundFP(double val, int digits);
diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc
index 1408dbac0..4a919ac27 100644
--- a/src/arch/mips/linux/process.cc
+++ b/src/arch/mips/linux/process.cc
@@ -33,7 +33,7 @@
#include "arch/mips/isa_traits.hh"
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "kern/linux/linux.hh"
#include "sim/process.hh"
@@ -45,9 +45,9 @@ using namespace MipsISA;
/// Target uname() handler.
static SyscallReturn
unameFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
+ TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0));
strcpy(name->sysname, "Linux");
strcpy(name->nodename, "m5.eecs.umich.edu");
@@ -55,7 +55,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "mips");
- name.copyOut(xc->getMemPort());
+ name.copyOut(tc->getMemPort());
return 0;
}
@@ -64,18 +64,18 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
/// different in practice from those used by Tru64 processes.
static SyscallReturn
sys_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- unsigned op = xc->getSyscallArg(0);
- // unsigned nbytes = xc->getSyscallArg(2);
+ unsigned op = tc->getSyscallArg(0);
+ // unsigned nbytes = tc->getSyscallArg(2);
switch (op) {
case 45: { // GSI_IEEE_FP_CONTROL
- TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
+ TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
*fpcr = 0;
- fpcr.copyOut(xc->getMemPort());
+ fpcr.copyOut(tc->getMemPort());
return 0;
}
@@ -91,17 +91,17 @@ sys_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
/// Target sys_setsysinfo() handler.
static SyscallReturn
sys_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- unsigned op = xc->getSyscallArg(0);
- // unsigned nbytes = xc->getSyscallArg(2);
+ unsigned op = tc->getSyscallArg(0);
+ // unsigned nbytes = tc->getSyscallArg(2);
switch (op) {
case 14: { // SSI_IEEE_FP_CONTROL
- TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
+ TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
- fpcr.copyIn(xc->getMemPort());
+ fpcr.copyIn(tc->getMemPort());
DPRINTFR(SyscallVerbose, "sys_setsysinfo(SSI_IEEE_FP_CONTROL): "
" setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
return 0;
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index 13d8ac3a8..bd7aa394e 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -34,7 +34,7 @@
#include "arch/mips/linux/process.hh"
#include "base/loader/object_file.hh"
#include "base/misc.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index 3781a91f3..013aa01c7 100644
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -40,7 +40,7 @@
#include "sim/host.hh"
class Checkpoint;
-class ExecContext;
+class ThreadContext;
class Regfile;
namespace MipsISA
diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh
index 2a0db38a4..dc82a3c26 100644
--- a/src/arch/mips/regfile/int_regfile.hh
+++ b/src/arch/mips/regfile/int_regfile.hh
@@ -37,7 +37,7 @@
#include "sim/faults.hh"
class Checkpoint;
-class ExecContext;
+class ThreadContext;
class Regfile;
namespace MipsISA
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 72aa17424..f8aeab8cb 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -36,7 +36,7 @@
#include "sim/faults.hh"
class Checkpoint;
-class ExecContext;
+class ThreadContext;
class Regfile;
namespace MipsISA
@@ -57,14 +57,14 @@ namespace MipsISA
int getInstAsid();
int getDataAsid();
- void copyMiscRegs(ExecContext *xc);
+ void copyMiscRegs(ThreadContext *tc);
MiscReg readReg(int misc_reg)
{
return miscRegFile[misc_reg];
}
- MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc)
+ MiscReg readRegWithEffect(int misc_reg, Fault &fault, ThreadContext *tc)
{
return miscRegFile[misc_reg];
}
@@ -75,7 +75,7 @@ namespace MipsISA
}
Fault setRegWithEffect(int misc_reg, const MiscReg &val,
- ExecContext *xc)
+ ThreadContext *tc)
{
miscRegFile[misc_reg] = val; return NoFault;
}
@@ -87,9 +87,9 @@ namespace MipsISA
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
private:
- MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { }
+ MiscReg readIpr(int idx, Fault &fault, ThreadContext *tc) { }
- Fault setIpr(int idx, uint64_t val, ExecContext *xc) { }
+ Fault setIpr(int idx, uint64_t val, ThreadContext *tc) { }
#endif
friend class RegFile;
};
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index e1b834568..af61e62cd 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -39,7 +39,7 @@
#include "sim/faults.hh"
class Checkpoint;
-class ExecContext;
+class ThreadContext;
namespace MipsISA
{
@@ -64,10 +64,10 @@ namespace MipsISA
}
MiscReg readMiscRegWithEffect(int miscReg,
- Fault &fault, ExecContext *xc)
+ Fault &fault, ThreadContext *tc)
{
fault = NoFault;
- return miscRegFile.readRegWithEffect(miscReg, fault, xc);
+ return miscRegFile.readRegWithEffect(miscReg, fault, tc);
}
Fault setMiscReg(int miscReg, const MiscReg &val)
@@ -76,9 +76,9 @@ namespace MipsISA
}
Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
- ExecContext * xc)
+ ThreadContext * tc)
{
- return miscRegFile.setRegWithEffect(miscReg, val, xc);
+ return miscRegFile.setRegWithEffect(miscReg, val, tc);
}
FloatReg readFloatReg(int floatReg)
@@ -189,12 +189,12 @@ namespace MipsISA
}
};
- void copyRegs(ExecContext *src, ExecContext *dest);
+ void copyRegs(ThreadContext *src, ThreadContext *dest);
- void copyMiscRegs(ExecContext *src, ExecContext *dest);
+ void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
#if FULL_SYSTEM
- void copyIprs(ExecContext *src, ExecContext *dest);
+ void copyIprs(ThreadContext *src, ThreadContext *dest);
#endif
} // namespace MipsISA
diff --git a/src/arch/mips/stacktrace.hh b/src/arch/mips/stacktrace.hh
index 3516b1d19..38767cef7 100644
--- a/src/arch/mips/stacktrace.hh
+++ b/src/arch/mips/stacktrace.hh
@@ -34,13 +34,13 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
-class ExecContext;
+class ThreadContext;
class StackTrace;
class ProcessInfo
{
private:
- ExecContext *xc;
+ ThreadContext *tc;
int thread_info_size;
int task_struct_size;
@@ -49,7 +49,7 @@ class ProcessInfo
int name_off;
public:
- ProcessInfo(ExecContext *_xc);
+ ProcessInfo(ThreadContext *_tc);
Addr task(Addr ksp) const;
int pid(Addr ksp) const;
@@ -61,7 +61,7 @@ class StackTrace
protected:
typedef TheISA::MachInst MachInst;
private:
- ExecContext *xc;
+ ThreadContext *tc;
std::vector<Addr> stack;
private:
@@ -70,21 +70,21 @@ class StackTrace
bool decodeSave(MachInst inst, int &reg, int &disp);
bool decodeStack(MachInst inst, int &disp);
- void trace(ExecContext *xc, bool is_call);
+ void trace(ThreadContext *tc, bool is_call);
public:
StackTrace();
- StackTrace(ExecContext *xc, StaticInstPtr inst);
+ StackTrace(ThreadContext *tc, StaticInstPtr inst);
~StackTrace();
void clear()
{
- xc = 0;
+ tc = 0;
stack.clear();
}
- bool valid() const { return xc != NULL; }
- bool trace(ExecContext *xc, StaticInstPtr inst);
+ bool valid() const { return tc != NULL; }
+ bool trace(ThreadContext *tc, StaticInstPtr inst);
public:
const std::vector<Addr> &getstack() const { return stack; }
@@ -106,7 +106,7 @@ class StackTrace
};
inline bool
-StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
+StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;
@@ -114,7 +114,7 @@ StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
if (valid())
clear();
- trace(xc, !inst->isReturn());
+ trace(tc, !inst->isReturn());
return true;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 05:39:51 +0000