diff options
Diffstat (limited to 'src/arch/mips')
| -rw-r--r-- | src/arch/mips/isa.hh | 12 | ||||
| -rw-r--r-- | src/arch/mips/registers.hh | 10 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh index c751cb168..c38b7cec0 100644 --- a/src/arch/mips/isa.hh +++ b/src/arch/mips/isa.hh @@ -180,6 +180,18 @@ namespace MipsISA return reg; } + int + flattenVecIndex(int reg) const + { + return reg; + } + + int + flattenVecElemIndex(int reg) const + { + return reg; + } + // dummy int flattenCCIndex(int reg) const diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh index c7cdb6522..f5dd325cd 100644 --- a/src/arch/mips/registers.hh +++ b/src/arch/mips/registers.hh @@ -32,6 +32,7 @@ #ifndef __ARCH_MIPS_REGISTERS_HH__ #define __ARCH_MIPS_REGISTERS_HH__ +#include "arch/generic/vec_reg.hh" #include "arch/mips/generated/max_inst_regs.hh" #include "base/misc.hh" #include "base/types.hh" @@ -289,6 +290,15 @@ typedef uint64_t MiscReg; // dummy typedef since we don't have CC regs typedef uint8_t CCReg; +// dummy typedefs since we don't have vector regs +constexpr unsigned NumVecElemPerVecReg = 2; +using VecElem = uint32_t; +using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; +using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; +using VecRegContainer = VecReg::Container; +// This has to be one to prevent warnings that are treated as errors +constexpr unsigned NumVecRegs = 1; + typedef union { IntReg intreg; FloatReg fpreg; |