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-rw-r--r--src/arch/mips/SConscript73
-rw-r--r--src/arch/mips/SConsopts33
-rw-r--r--src/arch/mips/faults.cc26
-rw-r--r--src/arch/mips/faults.hh24
-rw-r--r--src/arch/mips/isa/decoder.isa7
-rw-r--r--src/arch/mips/isa/formats/mem.isa71
-rw-r--r--src/arch/mips/isa/formats/util.isa6
-rw-r--r--src/arch/mips/linux/linux.hh18
-rw-r--r--src/arch/mips/predecoder.hh100
-rw-r--r--src/arch/mips/regfile/misc_regfile.hh8
-rw-r--r--src/arch/mips/regfile/regfile.hh16
-rw-r--r--src/arch/mips/types.hh2
-rw-r--r--src/arch/mips/utility.hh16
13 files changed, 260 insertions, 140 deletions
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 8353bcde7..f959951b3 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -30,54 +30,25 @@
# Steve Reinhardt
# Korey Sewell
-import os
-import sys
-from os.path import isdir
-
-# Import build environment variable from SConstruct.
-Import('env')
-
-###################################################
-#
-# Define needed sources.
-#
-###################################################
-
-# Base sources used by all configurations.
-base_sources = Split('''
- faults.cc
- isa_traits.cc
- utility.cc
- ''')
-
-# Full-system sources
-full_system_sources = Split('''
- #Insert Full-System Files Here
- ''')
-
-# Syscall emulation (non-full-system) sources
-syscall_emulation_sources = Split('''
- linux/linux.cc
- linux/process.cc
- process.cc
- ''')
-
-# Set up complete list of sources based on configuration.
-sources = base_sources
-
-if env['FULL_SYSTEM']:
- sources += full_system_sources
-else:
- sources += syscall_emulation_sources
-
-# Convert file names to SCons File objects. This takes care of the
-# path relative to the top of the directory tree.
-sources = [File(s) for s in sources]
-
-# Add in files generated by the ISA description.
-isa_desc_files = env.ISADesc('isa/main.isa')
-# Only non-header files need to be compiled.
-isa_desc_sources = [f for f in isa_desc_files if not f.path.endswith('.hh')]
-sources += isa_desc_sources
-
-Return('sources')
+Import('*')
+
+if env['TARGET_ISA'] == 'mips':
+ Source('faults.cc')
+ Source('isa_traits.cc')
+ Source('utility.cc')
+
+ if env['FULL_SYSTEM']:
+ #Insert Full-System Files Here
+ pass
+ else:
+ Source('process.cc')
+
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+
+ # Add in files generated by the ISA description.
+ isa_desc_files = env.ISADesc('isa/main.isa')
+ # Only non-header files need to be compiled.
+ for f in isa_desc_files:
+ if not f.path.endswith('.hh'):
+ Source(f)
diff --git a/src/arch/mips/SConsopts b/src/arch/mips/SConsopts
new file mode 100644
index 000000000..744fc9cca
--- /dev/null
+++ b/src/arch/mips/SConsopts
@@ -0,0 +1,33 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+Import('*')
+
+all_isa_list.append('mips')
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 2a8ab1df5..c9e6aa75b 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -58,12 +58,6 @@ FaultName ArithmeticFault::_name = "arith";
FaultVect ArithmeticFault::_vect = 0x0501;
FaultStat ArithmeticFault::_count;
-#if !FULL_SYSTEM
-FaultName PageTableFault::_name = "page_table_fault";
-FaultVect PageTableFault::_vect = 0x0000;
-FaultStat PageTableFault::_count;
-#endif
-
FaultName InterruptFault::_name = "interrupt";
FaultVect InterruptFault::_vect = 0x0101;
FaultStat InterruptFault::_count;
@@ -112,25 +106,5 @@ FaultName IntegerOverflowFault::_name = "intover";
FaultVect IntegerOverflowFault::_vect = 0x0501;
FaultStat IntegerOverflowFault::_count;
-void PageTableFault::invoke(ThreadContext *tc)
-{
- Process *p = tc->getProcessPtr();
-
- // address is higher than the stack region or in the current stack region
- if (vaddr > p->stack_base || vaddr > p->stack_min)
- FaultBase::invoke(tc);
-
- // We've accessed the next page
- if (vaddr > p->stack_min - PageBytes) {
- p->stack_min -= PageBytes;
- if (p->stack_base - p->stack_min > 8*1024*1024)
- fatal("Over max stack size for one thread\n");
- p->pTable->allocate(p->stack_min, PageBytes);
- warn("Increasing stack size by one page.");
- } else {
- FaultBase::invoke(tc);
- }
-}
-
} // namespace MipsISA
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 9d2c5df32..86c742413 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -80,30 +80,6 @@ class AlignmentFault : public MipsFault
bool isAlignmentFault() {return true;}
};
-#if !FULL_SYSTEM
-class PageTableFault : public MipsFault
-{
- private:
- Addr vaddr;
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
- public:
- PageTableFault(Addr va)
- : vaddr(va) {}
- FaultName name() {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
- void invoke(ThreadContext * tc);
-};
-
-static inline Fault genPageTableFault(Addr va)
-{
- return new PageTableFault(va);
-}
-#endif
-
-
static inline Fault genMachineCheckFault()
{
return new MachineCheckFault;
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 99c9e1604..b5d1df4fc 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -289,8 +289,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode RS_MSB {
0x0: decode RS {
format CP0Control {
- 0x0: mfc0({{ Rt = xc->readMiscReg(RD << 5 | SEL); }});
- 0x4: mtc0({{ xc->setMiscReg(RD << 5 | SEL, Rt); }});
+ 0x0: mfc0({{ Rt = xc->readMiscRegNoEffect(RD << 5 | SEL); }});
+ 0x4: mtc0({{ xc->setMiscRegNoEffect(RD << 5 | SEL, Rt); }});
}
format MipsMT {
@@ -1093,6 +1093,9 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
{{ uint64_t tmp = write_result;
Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
+ if (tmp == 1) {
+ xc->setStCondFailures(0);
+ }
}}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
format StoreMemory {
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index fccda2775..df80e7a1f 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -325,6 +325,41 @@ def template StoreMemAccExecute {{
{
Addr EA;
Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ EA = xc->getEA();
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+ memAccessFlags, NULL);
+ if (traceData) { traceData->setData(Mem); }
+ }
+
+ if (fault == NoFault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
+def template StoreCondMemAccExecute {{
+ Fault
+ %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@@ -361,6 +396,40 @@ def template StoreExecute {{
{
Addr EA;
Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+ memAccessFlags, NULL);
+ if (traceData) { traceData->setData(Mem); }
+ }
+
+ if (fault == NoFault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
+def template StoreCondExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@@ -449,7 +518,7 @@ def template StoreCondCompleteAcc {{
%(fp_enable_check)s;
%(op_dest_decl)s;
- uint64_t write_result = pkt->req->getScResult();
+ uint64_t write_result = pkt->req->getExtraData();
if (fault == NoFault) {
%(postacc_code)s;
diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa
index ec524113d..884e6f727 100644
--- a/src/arch/mips/isa/formats/util.isa
+++ b/src/arch/mips/isa/formats/util.isa
@@ -66,10 +66,8 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
# select templates
- # define aliases... most StoreCond templates are the same as the
- # corresponding Store templates (only CompleteAcc is different).
- StoreCondMemAccExecute = StoreMemAccExecute
- StoreCondExecute = StoreExecute
+ # The InitiateAcc template is the same for StoreCond templates as the
+ # corresponding Store template..
StoreCondInitiateAcc = StoreInitiateAcc
memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
diff --git a/src/arch/mips/linux/linux.hh b/src/arch/mips/linux/linux.hh
index f85935bb9..a20221e9b 100644
--- a/src/arch/mips/linux/linux.hh
+++ b/src/arch/mips/linux/linux.hh
@@ -91,15 +91,15 @@ class MipsLinux : public Linux
//@{
/// ioctl() command codes.
- static const unsigned TIOCGETP = 0x7408;
- static const unsigned TIOCSETP = 0x7409;
- static const unsigned TIOCSETN = 0x740a;
- static const unsigned TIOCSETC = 0x7411;
- static const unsigned TIOCGETC = 0x7412;
- static const unsigned FIONREAD = 0x467f;
- static const unsigned TIOCISATTY = 0x5480;
- static const unsigned TIOCGETS = 0x7413;
- static const unsigned TIOCGETA = 0x7417;
+ static const unsigned TIOCGETP_ = 0x7408;
+ static const unsigned TIOCSETP_ = 0x7409;
+ static const unsigned TIOCSETN_ = 0x740a;
+ static const unsigned TIOCSETC_ = 0x7411;
+ static const unsigned TIOCGETC_ = 0x7412;
+ static const unsigned FIONREAD_ = 0x467f;
+ static const unsigned TIOCISATTY_ = 0x5480;
+ static const unsigned TIOCGETS_ = 0x7413;
+ static const unsigned TIOCGETA_ = 0x7417;
//@}
/// For table().
diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh
new file mode 100644
index 000000000..a25cce8a7
--- /dev/null
+++ b/src/arch/mips/predecoder.hh
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_MIPS_PREDECODER_HH__
+#define __ARCH_MIPS_PREDECODER_HH__
+
+#include "arch/mips/types.hh"
+#include "base/misc.hh"
+#include "sim/host.hh"
+
+class ThreadContext;
+
+namespace MipsISA
+{
+ class Predecoder
+ {
+ protected:
+ ThreadContext * tc;
+ //The extended machine instruction being generated
+ ExtMachInst emi;
+
+ public:
+ Predecoder(ThreadContext * _tc) : tc(_tc)
+ {}
+
+ ThreadContext * getTC()
+ {
+ return tc;
+ }
+
+ void setTC(ThreadContext * _tc)
+ {
+ tc = _tc;
+ }
+
+ void process()
+ {
+ }
+
+ //Use this to give data to the predecoder. This should be used
+ //when there is control flow.
+ void moreBytes(Addr currPC, Addr off, MachInst inst)
+ {
+ assert(off == 0);
+ emi = inst;
+ }
+
+ //Use this to give data to the predecoder. This should be used
+ //when instructions are executed in order.
+ void moreBytes(MachInst machInst)
+ {
+ moreBytes(0, 0, machInst);
+ }
+
+ bool needMoreBytes()
+ {
+ return true;
+ }
+
+ bool extMachInstReady()
+ {
+ return true;
+ }
+
+ //This returns a constant reference to the ExtMachInst to avoid a copy
+ const ExtMachInst & getExtMachInst()
+ {
+ return emi;
+ }
+ };
+};
+
+#endif // __ARCH_MIPS_PREDECODER_HH__
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 368925e00..53ee09512 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -215,22 +215,22 @@ namespace MipsISA
void copyMiscRegs(ThreadContext *tc);
- MiscReg readReg(int misc_reg)
+ MiscReg readRegNoEffect(int misc_reg)
{
return miscRegFile[misc_reg];
}
- MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc)
+ MiscReg readReg(int misc_reg, ThreadContext *tc)
{
return miscRegFile[misc_reg];
}
- void setReg(int misc_reg, const MiscReg &val)
+ void setRegNoEffect(int misc_reg, const MiscReg &val)
{
miscRegFile[misc_reg] = val;
}
- void setRegWithEffect(int misc_reg, const MiscReg &val,
+ void setReg(int misc_reg, const MiscReg &val,
ThreadContext *tc)
{
miscRegFile[misc_reg] = val;
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 7b57b31f5..387fbd5c8 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -57,25 +57,25 @@ namespace MipsISA
bzero(&miscRegFile, sizeof(miscRegFile));
}
- MiscReg readMiscReg(int miscReg)
+ MiscReg readMiscRegNoEffect(int miscReg)
{
- return miscRegFile.readReg(miscReg);
+ return miscRegFile.readRegNoEffect(miscReg);
}
- MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc)
+ MiscReg readMiscReg(int miscReg, ThreadContext *tc)
{
- return miscRegFile.readRegWithEffect(miscReg, tc);
+ return miscRegFile.readReg(miscReg, tc);
}
- void setMiscReg(int miscReg, const MiscReg &val)
+ void setMiscRegNoEffect(int miscReg, const MiscReg &val)
{
- miscRegFile.setReg(miscReg, val);
+ miscRegFile.setRegNoEffect(miscReg, val);
}
- void setMiscRegWithEffect(int miscReg, const MiscReg &val,
+ void setMiscReg(int miscReg, const MiscReg &val,
ThreadContext * tc)
{
- miscRegFile.setRegWithEffect(miscReg, val, tc);
+ miscRegFile.setReg(miscReg, val, tc);
}
FloatRegVal readFloatReg(int floatReg)
diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh
index d4fa296fd..fc45ea253 100644
--- a/src/arch/mips/types.hh
+++ b/src/arch/mips/types.hh
@@ -40,6 +40,8 @@ namespace MipsISA
typedef uint8_t RegIndex;
typedef uint32_t IntReg;
+ typedef uint64_t LargestRead;
+
// floating point register file entry type
typedef uint32_t FloatReg32;
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 56689ba4d..12db1de57 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -27,6 +28,7 @@
*
* Authors: Nathan Binkert
* Steve Reinhardt
+ * Korey Sewell
*/
#ifndef __ARCH_MIPS_UTILITY_HH__
@@ -86,17 +88,9 @@ namespace MipsISA {
return 0;
}
- static inline ExtMachInst
- makeExtMI(MachInst inst, ThreadContext * xc) {
-#if FULL_SYSTEM
- ExtMachInst ext_inst = inst;
- if (xc->readPC() && 0x1)
- return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32);
- else
- return ext_inst;
-#else
- return ExtMachInst(inst);
-#endif
+ inline void startupCPU(ThreadContext *tc, int cpuId)
+ {
+ tc->activate(0);
}
};
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