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-rw-r--r--src/arch/mips/tlb.cc6
-rw-r--r--src/arch/mips/tlb.hh1
2 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 49ff2caba..8b106d437 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -346,6 +346,12 @@ TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
return NoFault;
}
+Fault
+TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+{
+ return NoFault;
+}
+
MipsISA::PTE &
TLB::index(bool advance)
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index e949d16d9..fdd590e85 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -118,6 +118,7 @@ class TLB : public BaseTLB
* support the Checker model at the moment.
*/
Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+ Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
private:
Fault translateInst(RequestPtr req, ThreadContext *tc);