summaryrefslogtreecommitdiff
path: root/src/arch/mips
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/mips')
-rw-r--r--src/arch/mips/locked_mem.hh4
-rw-r--r--src/arch/mips/tlb.cc13
-rw-r--r--src/arch/mips/tlb.hh13
3 files changed, 16 insertions, 14 deletions
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 7fa1642a8..05d637ba7 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -75,7 +75,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
template <class XC>
inline void
-handleLockedRead(XC *xc, RequestPtr req)
+handleLockedRead(XC *xc, const RequestPtr &req)
{
xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
xc->setMiscReg(MISCREG_LLFLAG, true);
@@ -92,7 +92,7 @@ handleLockedSnoopHit(XC *xc)
template <class XC>
inline bool
-handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
{
if (req->isUncacheable()) {
// Funky Turbolaser mailbox access...don't update
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index a18149dfa..46e250b2b 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -142,7 +142,7 @@ TLB::probeEntry(Addr vpn, uint8_t asn) const
}
inline Fault
-TLB::checkCacheability(RequestPtr &req)
+TLB::checkCacheability(const RequestPtr &req)
{
Addr VAddrUncacheable = 0xA0000000;
// In MIPS, cacheability is controlled by certain bits of the virtual
@@ -282,7 +282,7 @@ TLB::regStats()
}
Fault
-TLB::translateInst(RequestPtr req, ThreadContext *tc)
+TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
{
if (FullSystem)
panic("translateInst not implemented in MIPS.\n");
@@ -297,7 +297,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
}
Fault
-TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
+TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
{
if (FullSystem)
panic("translateData not implemented in MIPS.\n");
@@ -312,7 +312,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
}
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
+TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
{
if (mode == Execute)
return translateInst(req, tc);
@@ -321,7 +321,7 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
}
void
-TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
Translation *translation, Mode mode)
{
assert(translation);
@@ -329,7 +329,8 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
}
Fault
-TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+TLB::finalizePhysical(const RequestPtr &req,
+ ThreadContext *tc, Mode mode) const
{
return NoFault;
}
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 626812af8..3a39747c0 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -104,7 +104,7 @@ class TLB : public BaseTLB
// static helper functions... really
static bool validVirtualAddress(Addr vaddr);
- static Fault checkCacheability(RequestPtr &req);
+ static Fault checkCacheability(const RequestPtr &req);
// Checkpointing
void serialize(CheckpointOut &cp) const override;
@@ -113,16 +113,17 @@ class TLB : public BaseTLB
void regStats() override;
Fault translateAtomic(
- RequestPtr req, ThreadContext *tc, Mode mode) override;
+ const RequestPtr &req, ThreadContext *tc, Mode mode) override;
void translateTiming(
- RequestPtr req, ThreadContext *tc,
+ const RequestPtr &req, ThreadContext *tc,
Translation *translation, Mode mode) override;
Fault finalizePhysical(
- RequestPtr req, ThreadContext *tc, Mode mode) const override;
+ const RequestPtr &req,
+ ThreadContext *tc, Mode mode) const override;
private:
- Fault translateInst(RequestPtr req, ThreadContext *tc);
- Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+ Fault translateInst(const RequestPtr &req, ThreadContext *tc);
+ Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
};
}