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-rw-r--r--src/arch/mips/tlb.cc5
-rw-r--r--src/arch/mips/tlb.hh1
2 files changed, 0 insertions, 6 deletions
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index e01c06ae5..cf1230745 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -281,11 +281,6 @@ TLB::regStats()
.desc("DTB misses")
;
- invalids
- .name(name() + ".invalids")
- .desc("DTB access violations")
- ;
-
accesses
.name(name() + ".accesses")
.desc("DTB accesses")
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 68b1c0c75..e301cf666 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -105,7 +105,6 @@ class TLB : public BaseTLB
mutable Stats::Scalar write_accesses;
Stats::Formula hits;
Stats::Formula misses;
- Stats::Formula invalids;
Stats::Formula accesses;
public: