diff options
Diffstat (limited to 'src/arch/mips')
-rw-r--r-- | src/arch/mips/tlb.cc | 7 | ||||
-rw-r--r-- | src/arch/mips/tlb.hh | 5 |
2 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index cd6d47d1e..49ff2caba 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -339,6 +339,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc, translation->finish(translateAtomic(req, tc, mode), req, tc, mode); } +Fault +TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) +{ + panic("Not implemented\n"); + return NoFault; +} + MipsISA::PTE & TLB::index(bool advance) diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index 834431536..e949d16d9 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -114,6 +114,11 @@ class TLB : public BaseTLB void translateTiming(RequestPtr req, ThreadContext *tc, Translation *translation, Mode mode); + /** Function stub for CheckerCPU compilation issues. MIPS does not + * support the Checker model at the moment. + */ + Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); + private: Fault translateInst(RequestPtr req, ThreadContext *tc); Fault translateData(RequestPtr req, ThreadContext *tc, bool write); |