2 files changed, 0 insertions, 16 deletions
diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index c91ee1e99..e04d22631 100755
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -156,12 +156,6 @@ static inline void setCauseIP_(ThreadContext *tc, uint8_t val) {
   return false;
   }
 
-
-  uint64_t Interrupts::get_vec(int int_num)
-  {
-  panic("MipsISA::Interrupts::get_vec() is not implemented. \n");
-  M5_DUMMY_RETURN
-  }
 */
 void Interrupts::post(int int_num, ThreadContext* tc)
 {
@@ -252,12 +246,6 @@ void Interrupts::updateIntrInfo(ThreadContext *tc) const
     ;
 }
 
-uint64_t Interrupts::get_vec(int int_num)
-{
-    panic("MipsISA::Interrupts::get_vec() is not implemented. \n");
-    M5_DUMMY_RETURN
-        }
-
 bool Interrupts::interruptsPending(ThreadContext *tc) const
 {
     //if there is a on cpu timer interrupt (i.e. Compare == Count)
diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh
index f0e928088..99a8f6fa0 100755
--- a/src/arch/mips/interrupts.hh
+++ b/src/arch/mips/interrupts.hh
@@ -91,8 +91,6 @@ class Interrupts
       void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
       bool onCpuTimerInterrupt(ThreadContext *tc) const;
 
-      uint64_t get_vec(int int_num);
-
       bool check_interrupts(ThreadContext * tc) const{
       //return (intstatus != 0) && !(tc->readPC() & 0x3);
       if (oncputimerintr == false){
@@ -160,8 +158,6 @@ class Interrupts
     bool interruptsPending(ThreadContext *tc) const;
     bool onCpuTimerInterrupt(ThreadContext *tc) const;
 
-    uint64_t get_vec(int int_num);
-
     bool check_interrupts(ThreadContext * tc) const{
         return interruptsPending(tc);
     }