diff options
Diffstat (limited to 'src/arch/mips')
24 files changed, 473 insertions, 1461 deletions
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index 0b470def6..ffc1f18eb 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -34,10 +34,7 @@ Import('*') if env['TARGET_ISA'] == 'mips': Source('faults.cc') - Source('regfile/int_regfile.cc') - Source('regfile/float_regfile.cc') - Source('regfile/misc_regfile.cc') - Source('regfile/regfile.cc') + Source('isa.cc') Source('tlb.cc') Source('pagetable.cc') Source('utility.cc') diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc index 63884e837..347d041a3 100644 --- a/src/arch/mips/faults.cc +++ b/src/arch/mips/faults.cc @@ -435,7 +435,6 @@ void InterruptFault::invoke(ThreadContext *tc) { #if FULL_SYSTEM DPRINTF(MipsPRA,"%s encountered.\n", name()); - //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil setExceptionState(tc,0x0A); Addr HandlerBase; @@ -471,7 +470,6 @@ void ReservedInstructionFault::invoke(ThreadContext *tc) { #if FULL_SYSTEM DPRINTF(MipsPRA,"%s encountered.\n", name()); - //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil setExceptionState(tc,0x0A); Addr HandlerBase; HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase); // Offset 0x180 - General Exception Vector diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/isa.cc index aee4fab4d..f03a72e98 100644 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/isa.cc @@ -1,6 +1,5 @@ /* - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. + * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,26 +25,22 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Korey Sewell - * Jaidev Patwardhan + * Authors: Gabe Black */ -#include "base/bitfield.hh" - -#include "arch/mips/regfile/misc_regfile.hh" +#include "arch/mips/isa.hh" #include "arch/mips/mt_constants.hh" +#include "arch/mips/mt.hh" #include "arch/mips/pra_constants.hh" - -#include "cpu/thread_context.hh" +#include "base/bitfield.hh" #include "cpu/base.hh" -#include "cpu/exetrace.hh" - -//#include "params/DerivO3CPU.hh" +#include "cpu/thread_context.hh" -using namespace std; -using namespace MipsISA; +namespace MipsISA +{ -std::string MiscRegFile::miscRegNames[NumMiscRegs] = +std::string +ISA::miscRegNames[NumMiscRegs] = { "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "", "Random", "VPEControl", "VPEConf0", "VPEConf1", @@ -91,19 +86,19 @@ std::string MiscRegFile::miscRegNames[NumMiscRegs] = "LLFlag" }; -MiscRegFile::MiscRegFile() +ISA::ISA() { init(); } -MiscRegFile::MiscRegFile(BaseCPU *_cpu) +ISA::ISA(BaseCPU *_cpu) { cpu = _cpu; init(); } void -MiscRegFile::init() +ISA::init() { miscRegFile.resize(NumMiscRegs); bankType.resize(NumMiscRegs); @@ -122,7 +117,7 @@ MiscRegFile::init() } void -MiscRegFile::clear(unsigned tid_or_vpn) +ISA::clear(unsigned tid_or_vpn) { for(int i = 0; i < NumMiscRegs; i++) { miscRegFile[i][tid_or_vpn] = 0; @@ -131,7 +126,7 @@ MiscRegFile::clear(unsigned tid_or_vpn) } void -MiscRegFile::expandForMultithreading(ThreadID num_threads, unsigned num_vpes) +ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes) { // Initialize all Per-VPE regs uint32_t per_vpe_regs[] = { VPEControl, VPEConf0, VPEConf1, YQMask, @@ -167,20 +162,10 @@ MiscRegFile::expandForMultithreading(ThreadID num_threads, unsigned num_vpes) } } -int MiscRegFile::getInstAsid() -{ - MiscReg Entry_Hi = readRegNoEffect(EntryHi); - return bits(Entry_Hi,EntryHi_ASID_HI,EntryHi_ASID_LO); -} -int MiscRegFile:: getDataAsid() -{ - MiscReg EHi = readRegNoEffect(EntryHi); - return bits(EHi,EntryHi_ASID_HI,EntryHi_ASID_LO); -} //@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H) void -MiscRegFile::reset(std::string core_name, ThreadID num_threads, +ISA::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes, BaseCPU *_cpu) { DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n", @@ -196,33 +181,33 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, // =================================================== DPRINTF(MipsPRA, "Initializing CP0 State.... "); - MiscReg ProcID = readRegNoEffect(PRId); + MiscReg ProcID = readMiscRegNoEffect(PRId); replaceBits(ProcID,PRIdCoOp_HI,PRIdCoOp_LO,cp.CP0_PRId_CompanyOptions); replaceBits(ProcID,PRIdCoID_HI,PRIdCoID_LO,cp.CP0_PRId_CompanyID); replaceBits(ProcID,PRIdProc_ID_HI,PRIdProc_ID_LO,cp.CP0_PRId_ProcessorID); replaceBits(ProcID,PRIdRev_HI,PRIdRev_LO,cp.CP0_PRId_Revision); - setRegNoEffect(PRId,ProcID); + setMiscRegNoEffect(PRId,ProcID); // Now, create Write Mask for ProcID register MiscReg ProcID_Mask = 0; // Read-Only register replaceBits(ProcID_Mask,0,32,0); setRegMask(PRId,ProcID_Mask); // Config - MiscReg cfg = readRegNoEffect(Config); + MiscReg cfg = readMiscRegNoEffect(Config); replaceBits(cfg, Config_BE_HI, Config_BE_LO, cp.CP0_Config_BE); replaceBits(cfg, Config_AT_HI, Config_AT_LO, cp.CP0_Config_AT); replaceBits(cfg, Config_AR_HI, Config_AR_LO, cp.CP0_Config_AR); replaceBits(cfg, Config_MT_HI, Config_MT_LO, cp.CP0_Config_MT); replaceBits(cfg, Config_VI_HI, Config_VI_LO, cp.CP0_Config_VI); replaceBits(cfg, Config_M, 1); - setRegNoEffect(Config, cfg); + setMiscRegNoEffect(Config, cfg); // Now, create Write Mask for Config register MiscReg cfg_Mask = 0x7FFF0007; replaceBits(cfg_Mask,0,32,0); setRegMask(Config,cfg_Mask); // Config1 - MiscReg cfg1 = readRegNoEffect(Config1); + MiscReg cfg1 = readMiscRegNoEffect(Config1); replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO, cp.CP0_Config1_MMU); replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, cp.CP0_Config1_IS); @@ -238,14 +223,14 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, replaceBits(cfg1, Config1_C2_HI, Config1_C2_LO, cp.CP0_Config1_C2); replaceBits(cfg1, Config1_PC_HI, Config1_PC_LO, cp.CP0_Config1_PC); replaceBits(cfg1, Config1_M, cp.CP0_Config1_M); - setRegNoEffect(Config1, cfg1); + setMiscRegNoEffect(Config1, cfg1); // Now, create Write Mask for Config register MiscReg cfg1_Mask = 0; // Read Only Register replaceBits(cfg1_Mask,0,32,0); setRegMask(Config1,cfg1_Mask); // Config2 - MiscReg cfg2 = readRegNoEffect(Config2); + MiscReg cfg2 = readMiscRegNoEffect(Config2); replaceBits(cfg2, Config2_TU_HI, Config2_TU_LO, cp.CP0_Config2_TU); replaceBits(cfg2, Config2_TS_HI, Config2_TS_LO, cp.CP0_Config2_TS); replaceBits(cfg2, Config2_TL_HI, Config2_TL_LO, cp.CP0_Config2_TL); @@ -255,14 +240,14 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, replaceBits(cfg2, Config2_SL_HI, Config2_SL_LO, cp.CP0_Config2_SL); replaceBits(cfg2, Config2_SA_HI, Config2_SA_LO, cp.CP0_Config2_SA); replaceBits(cfg2, Config2_M, cp.CP0_Config2_M); - setRegNoEffect(Config2, cfg2); + setMiscRegNoEffect(Config2, cfg2); // Now, create Write Mask for Config register MiscReg cfg2_Mask = 0x7000F000; // Read Only Register replaceBits(cfg2_Mask,0,32,0); setRegMask(Config2,cfg2_Mask); // Config3 - MiscReg cfg3 = readRegNoEffect(Config3); + MiscReg cfg3 = readMiscRegNoEffect(Config3); replaceBits(cfg3, Config3_DSPP_HI, Config3_DSPP_LO, cp.CP0_Config3_DSPP); replaceBits(cfg3, Config3_LPA_HI, Config3_LPA_LO, cp.CP0_Config3_LPA); replaceBits(cfg3, Config3_VEIC_HI, Config3_VEIC_LO, cp.CP0_Config3_VEIC); @@ -271,17 +256,17 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, replaceBits(cfg3, Config3_MT_HI, Config3_MT_LO, cp.CP0_Config3_MT); replaceBits(cfg3, Config3_SM_HI, Config3_SM_LO, cp.CP0_Config3_SM); replaceBits(cfg3, Config3_TL_HI, Config3_TL_LO, cp.CP0_Config3_TL); - setRegNoEffect(Config3, cfg3); + setMiscRegNoEffect(Config3, cfg3); // Now, create Write Mask for Config register MiscReg cfg3_Mask = 0; // Read Only Register replaceBits(cfg3_Mask,0,32,0); setRegMask(Config3,cfg3_Mask); // EBase - CPUNum - MiscReg EB = readRegNoEffect(EBase); + MiscReg EB = readMiscRegNoEffect(EBase); replaceBits(EB, EBase_CPUNum_HI, EBase_CPUNum_LO, cp.CP0_EBase_CPUNum); replaceBits(EB, 31, 31, 1); - setRegNoEffect(EBase, EB); + setMiscRegNoEffect(EBase, EB); // Now, create Write Mask for Config register MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the // entire register is read only @@ -289,63 +274,63 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, setRegMask(EBase,EB_Mask); // SRS Control - HSS (Highest Shadow Set) - MiscReg SC = readRegNoEffect(SRSCtl); + MiscReg SC = readMiscRegNoEffect(SRSCtl); replaceBits(SC, SRSCtl_HSS_HI,SRSCtl_HSS_LO,cp.CP0_SrsCtl_HSS); - setRegNoEffect(SRSCtl, SC); + setMiscRegNoEffect(SRSCtl, SC); // Now, create Write Mask for the SRS Ctl register MiscReg SC_Mask = 0x0000F3C0; replaceBits(SC_Mask,0,32,0); setRegMask(SRSCtl,SC_Mask); // IntCtl - IPTI, IPPCI - MiscReg IC = readRegNoEffect(IntCtl); + MiscReg IC = readMiscRegNoEffect(IntCtl); replaceBits(IC, IntCtl_IPTI_HI,IntCtl_IPTI_LO,cp.CP0_IntCtl_IPTI); replaceBits(IC, IntCtl_IPPCI_HI,IntCtl_IPPCI_LO,cp.CP0_IntCtl_IPPCI); - setRegNoEffect(IntCtl, IC); + setMiscRegNoEffect(IntCtl, IC); // Now, create Write Mask for the IntCtl register MiscReg IC_Mask = 0x000003E0; replaceBits(IC_Mask,0,32,0); setRegMask(IntCtl,IC_Mask); // Watch Hi - M - FIXME (More than 1 Watch register) - MiscReg WHi = readRegNoEffect(WatchHi0); + MiscReg WHi = readMiscRegNoEffect(WatchHi0); replaceBits(WHi, WatchHi_M, cp.CP0_WatchHi_M); - setRegNoEffect(WatchHi0, WHi); + setMiscRegNoEffect(WatchHi0, WHi); // Now, create Write Mask for the IntCtl register MiscReg wh_Mask = 0x7FFF0FFF; replaceBits(wh_Mask,0,32,0); setRegMask(WatchHi0,wh_Mask); // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair) - MiscReg PCtr = readRegNoEffect(PerfCnt0); + MiscReg PCtr = readMiscRegNoEffect(PerfCnt0); replaceBits(PCtr, PerfCntCtl_M, cp.CP0_PerfCtr_M); replaceBits(PCtr, PerfCntCtl_W, cp.CP0_PerfCtr_W); - setRegNoEffect(PerfCnt0, PCtr); + setMiscRegNoEffect(PerfCnt0, PCtr); // Now, create Write Mask for the IntCtl register MiscReg pc_Mask = 0x00007FF; replaceBits(pc_Mask,0,32,0); setRegMask(PerfCnt0,pc_Mask); // Random - MiscReg random = readRegNoEffect(CP0_Random); + MiscReg random = readMiscRegNoEffect(CP0_Random); random = 63; - setRegNoEffect(CP0_Random, random); + setMiscRegNoEffect(CP0_Random, random); // Now, create Write Mask for the IntCtl register MiscReg random_Mask = 0; replaceBits(random_Mask,0,32,0); setRegMask(CP0_Random,random_Mask); // PageGrain - MiscReg pagegrain = readRegNoEffect(PageGrain); + MiscReg pagegrain = readMiscRegNoEffect(PageGrain); replaceBits(pagegrain,PageGrain_ESP,cp.CP0_Config3_SP); - setRegNoEffect(PageGrain, pagegrain); + setMiscRegNoEffect(PageGrain, pagegrain); // Now, create Write Mask for the IntCtl register MiscReg pg_Mask = 0x10000000; replaceBits(pg_Mask,0,32,0); setRegMask(PageGrain,pg_Mask); // Status - MiscReg stat = readRegNoEffect(Status); + MiscReg stat = readMiscRegNoEffect(Status); // Only CU0 and IE are modified on a reset - everything else needs // to be controlled on a per CPU model basis @@ -358,7 +343,7 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, // Enable BEV bit on a reset replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1); - setRegNoEffect(Status, stat); + setMiscRegNoEffect(Status, stat); // Now, create Write Mask for the Status register MiscReg stat_Mask = 0xFF78FF17; replaceBits(stat_Mask,0,32,0); @@ -366,45 +351,45 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, // MVPConf0 - MiscReg mvp_conf0 = readRegNoEffect(MVPConf0); + MiscReg mvp_conf0 = readMiscRegNoEffect(MVPConf0); replaceBits(mvp_conf0, MVPC0_TCA, 1); replaceBits(mvp_conf0, MVPC0_PVPE_HI, MVPC0_PVPE_LO, num_vpes - 1); replaceBits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO, num_threads - 1); - setRegNoEffect(MVPConf0, mvp_conf0); + setMiscRegNoEffect(MVPConf0, mvp_conf0); // VPEConf0 - MiscReg vpe_conf0 = readRegNoEffect(VPEConf0); + MiscReg vpe_conf0 = readMiscRegNoEffect(VPEConf0); replaceBits(vpe_conf0, VPEC0_MVP, 1); - setRegNoEffect(VPEConf0, vpe_conf0); + setMiscRegNoEffect(VPEConf0, vpe_conf0); // TCBind for (ThreadID tid = 0; tid < num_threads; tid++) { - MiscReg tc_bind = readRegNoEffect(TCBind, tid); + MiscReg tc_bind = readMiscRegNoEffect(TCBind, tid); replaceBits(tc_bind, TCB_CUR_TC_HI, TCB_CUR_TC_LO, tid); - setRegNoEffect(TCBind, tc_bind, tid); + setMiscRegNoEffect(TCBind, tc_bind, tid); } // TCHalt - MiscReg tc_halt = readRegNoEffect(TCHalt); + MiscReg tc_halt = readMiscRegNoEffect(TCHalt); replaceBits(tc_halt, TCH_H, 0); - setRegNoEffect(TCHalt, tc_halt); + setMiscRegNoEffect(TCHalt, tc_halt); /*for (ThreadID tid = 1; tid < num_threads; tid++) { // Set TCHalt Halt bit to 1 for all other threads - tc_halt = readRegNoEffect(TCHalt, tid); + tc_halt = readMiscRegNoEffect(TCHalt, tid); replaceBits(tc_halt, TCH_H, 1); setReg(TCHalt, tc_halt, tid); }*/ // TCStatus // Set TCStatus Activated to 1 for the initial thread that is running - MiscReg tc_status = readRegNoEffect(TCStatus); + MiscReg tc_status = readMiscRegNoEffect(TCStatus); replaceBits(tc_status, TCS_A, 1); - setRegNoEffect(TCStatus, tc_status); + setMiscRegNoEffect(TCStatus, tc_status); // Set Dynamically Allocatable bit to 1 for all other threads for (ThreadID tid = 1; tid < num_threads; tid++) { - tc_status = readRegNoEffect(TCStatus, tid); + tc_status = readMiscRegNoEffect(TCStatus, tid); replaceBits(tc_status, TCSTATUS_DA, 1); - setRegNoEffect(TCStatus, tc_status, tid); + setMiscRegNoEffect(TCStatus, tc_status, tid); } @@ -439,14 +424,14 @@ MiscRegFile::reset(std::string core_name, ThreadID num_threads, } inline unsigned -MiscRegFile::getVPENum(ThreadID tid) +ISA::getVPENum(ThreadID tid) { unsigned tc_bind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid]; return bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO); } MiscReg -MiscRegFile::readRegNoEffect(int reg_idx, ThreadID tid) +ISA::readMiscRegNoEffect(int reg_idx, ThreadID tid) { int misc_reg = reg_idx - Ctrl_Base_DepTag; unsigned reg_sel = (bankType[misc_reg] == perThreadContext) @@ -461,7 +446,7 @@ MiscRegFile::readRegNoEffect(int reg_idx, ThreadID tid) // Status to TCStatus depending on current thread //template <class TC> MiscReg -MiscRegFile::readReg(int reg_idx, ThreadContext *tc, ThreadID tid) +ISA::readMiscReg(int reg_idx, ThreadContext *tc, ThreadID tid) { int misc_reg = reg_idx - Ctrl_Base_DepTag; unsigned reg_sel = (bankType[misc_reg] == perThreadContext) @@ -480,7 +465,7 @@ MiscRegFile::readReg(int reg_idx, ThreadContext *tc, ThreadID tid) } void -MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid) +ISA::setMiscRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid) { int misc_reg = reg_idx - Ctrl_Base_DepTag; unsigned reg_sel = (bankType[misc_reg] == perThreadContext) @@ -492,8 +477,9 @@ MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid) miscRegFile[misc_reg][reg_sel] = val; } + void -MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid) +ISA::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid) { // return; int misc_reg = reg_idx - Ctrl_Base_DepTag; @@ -511,7 +497,7 @@ MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid) // with care! //template <class TC> void -MiscRegFile::setReg(int reg_idx, const MiscReg &val, +ISA::setMiscReg(int reg_idx, const MiscReg &val, ThreadContext *tc, ThreadID tid) { int misc_reg = reg_idx - Ctrl_Base_DepTag; @@ -529,13 +515,14 @@ MiscRegFile::setReg(int reg_idx, const MiscReg &val, scheduleCP0Update(1); } + /** * This method doesn't need to adjust the Control Register Offset * since it has already been done in the calling method * (setRegWithEffect) */ MiscReg -MiscRegFile::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) +ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) { MiscReg retVal = val; @@ -553,8 +540,9 @@ MiscRegFile::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) val, miscRegFile[misc_reg][reg_sel], retVal); return retVal; } + void -MiscRegFile::scheduleCP0Update(int delay) +ISA::scheduleCP0Update(int delay) { if (!cp0Updated) { cp0Updated = true; @@ -566,19 +554,19 @@ MiscRegFile::scheduleCP0Update(int delay) } void -MiscRegFile::updateCPU() +ISA::updateCPU() { /////////////////////////////////////////////////////////////////// // // EVALUATE CP0 STATE FOR MIPS MT // /////////////////////////////////////////////////////////////////// - unsigned mvp_conf0 = readRegNoEffect(MVPConf0); + unsigned mvp_conf0 = readMiscRegNoEffect(MVPConf0); ThreadID num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1; for (ThreadID tid = 0; tid < num_threads; tid++) { - MiscReg tc_status = readRegNoEffect(TCStatus, tid); - MiscReg tc_halt = readRegNoEffect(TCHalt, tid); + MiscReg tc_status = readMiscRegNoEffect(TCStatus, tid); + MiscReg tc_halt = readMiscRegNoEffect(TCHalt, tid); //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs if (bits(tc_halt, TCH_H) == 1 || bits(tc_status, TCS_A) == 0) { @@ -594,12 +582,12 @@ MiscRegFile::updateCPU() cp0Updated = false; } -MiscRegFile::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type) +ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type) : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type) { } void -MiscRegFile::CP0Event::process() +ISA::CP0Event::process() { switch (cp0EventType) { @@ -612,20 +600,22 @@ MiscRegFile::CP0Event::process() } const char * -MiscRegFile::CP0Event::description() const +ISA::CP0Event::description() const { return "Coprocessor-0 event"; } void -MiscRegFile::CP0Event::scheduleEvent(int delay) +ISA::CP0Event::scheduleEvent(int delay) { cpu->reschedule(this, curTick + cpu->ticks(delay), true); } void -MiscRegFile::CP0Event::unscheduleEvent() +ISA::CP0Event::unscheduleEvent() { if (scheduled()) squash(); } + +} diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/isa.hh index 633ea7efb..15c043dc0 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/isa.hh @@ -1,6 +1,5 @@ /* - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. + * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,33 +25,33 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Korey Sewell - * Jaidev Patwardhan + * Authors: Gabe Black */ -#ifndef __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__ -#define __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__ +#ifndef __ARCH_MIPS_ISA_HH__ +#define __ARCH_MIPS_ISA_HH__ -#include "arch/mips/isa_traits.hh" +#include <string> +#include <queue> +#include <vector> + +#include "arch/mips/registers.hh" #include "arch/mips/types.hh" -#include "arch/mips/mt.hh" -#include "arch/mips/mt_constants.hh" -#include "base/bitfield.hh" #include "sim/eventq.hh" -#include <queue> +#include "sim/faults.hh" -class Params; class BaseCPU; +class Checkpoint; +class EventManager; +class ThreadContext; namespace MipsISA { - class MiscRegFile { + class ISA + { public: - // Give RegFile object, private access - friend class RegFile; - // The MIPS name for this file is CP0 or Coprocessor 0 - typedef MiscRegFile CP0; + typedef ISA CP0; protected: enum BankType { @@ -68,8 +67,8 @@ namespace MipsISA BaseCPU *cpu; public: - MiscRegFile(); - MiscRegFile(BaseCPU *_cpu); + ISA(); + ISA(BaseCPU *_cpu); void init(); @@ -91,23 +90,20 @@ namespace MipsISA //@TODO: MIPS MT's register view automatically connects // Status to TCStatus depending on current thread void updateCP0ReadView(int misc_reg, ThreadID tid) { } - MiscReg readRegNoEffect(int misc_reg, ThreadID tid = 0); + MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); //template <class TC> - MiscReg readReg(int misc_reg, - ThreadContext *tc, ThreadID tid = 0); + MiscReg readMiscReg(int misc_reg, + ThreadContext *tc, ThreadID tid = 0); MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val); void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0); - void setRegNoEffect(int misc_reg, const MiscReg &val, - ThreadID tid = 0); + void setMiscRegNoEffect(int misc_reg, const MiscReg &val, + ThreadID tid = 0); //template <class TC> - void setReg(int misc_reg, const MiscReg &val, - ThreadContext *tc, ThreadID tid = 0); - - int getInstAsid(); - int getDataAsid(); + void setMiscReg(int misc_reg, const MiscReg &val, + ThreadContext *tc, ThreadID tid = 0); ////////////////////////////////////////////////////////// // @@ -128,7 +124,7 @@ namespace MipsISA class CP0Event : public Event { protected: - MiscRegFile::CP0 *cp0; + ISA::CP0 *cp0; BaseCPU *cpu; CP0EventType cp0EventType; Fault fault; @@ -161,7 +157,24 @@ namespace MipsISA std::queue<CP0Event*> cp0EventRemoveList; static std::string miscRegNames[NumMiscRegs]; + + public: + + int + flattenIntIndex(int reg) + { + return reg; + } + + int + flattenFloatIndex(int reg) + { + return reg; + } + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); }; -} // namespace MipsISA +} #endif diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index 74200a74a..52fcd0724 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -104,25 +104,14 @@ output exec {{ Trace::InstRecord *traceData) { uint64_t mips_nan = 0; - T src_op = 0; - int size = sizeof(src_op) * 8; + assert(sizeof(T) == 4); for (int i = 0; i < inst->numSrcRegs(); i++) { - uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size); - - if (isNan(&src_bits, size) ) { - if (isSnan(&src_bits, size)) { - switch (size) - { - case 32: mips_nan = MIPS32_QNAN; break; - case 64: mips_nan = MIPS64_QNAN; break; - default: panic("Unsupported Floating Point Size (%d)", size); - } - } else { - mips_nan = src_bits; - } + uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0); - xc->setFloatRegOperandBits(inst, 0, mips_nan, size); + if (isNan(&src_bits, 32) ) { + mips_nan = MIPS32_QNAN; + xc->setFloatRegOperandBits(inst, 0, mips_nan); if (traceData) { traceData->setData(mips_nan); } return true; } @@ -137,18 +126,13 @@ output exec {{ { uint64_t mips_nan = 0; T src_op = dest_val; - int size = sizeof(src_op) * 8; + assert(sizeof(T) == 4); - if (isNan(&src_op, size)) { - switch (size) - { - case 32: mips_nan = MIPS32_QNAN; break; - case 64: mips_nan = MIPS64_QNAN; break; - default: panic("Unsupported Floating Point Size (%d)", size); - } + if (isNan(&src_op, 32)) { + mips_nan = MIPS32_QNAN; //Set value to QNAN - cpu->setFloatRegOperandBits(inst, 0, mips_nan, size); + cpu->setFloatRegOperandBits(inst, 0, mips_nan); //Read FCSR from FloatRegFile uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa index aa1c8d8af..22eb3bf13 100644 --- a/src/arch/mips/isa/includes.isa +++ b/src/arch/mips/isa/includes.isa @@ -70,6 +70,7 @@ output exec {{ #include "arch/mips/isa_traits.hh" #include "arch/mips/utility.hh" #include "arch/mips/dsp.hh" +#include "arch/mips/mt.hh" #include "arch/mips/pra_constants.hh" #include "arch/mips/dt_constants.hh" #include "arch/mips/mt_constants.hh" diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa index 609708a13..c2733be9d 100644 --- a/src/arch/mips/isa/operands.isa +++ b/src/arch/mips/isa/operands.isa @@ -113,10 +113,7 @@ def operands {{ 'Index':('ControlReg','uw','MipsISA::Index',None,1), - #Special cases for when a Control Register Access is dependent on - #a combination of bitfield indices (handles MTCO & MFCO) - # Fixed to allow CP0 Register Offset - 'CP0_RD_SEL': ('IControlReg', 'uw', '(RD << 3 | SEL) + Ctrl_Base_DepTag', None, 1), + 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1), #MT Control Regs 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1), diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index 7522dcf0f..a8d5b07b6 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -143,7 +143,6 @@ namespace MipsISA NumInterruptLevels = INTLEVEL_EXTERNAL_MAX }; - // MIPS modes enum mode_type { @@ -154,53 +153,9 @@ namespace MipsISA mode_number // number of modes }; - inline mode_type getOperatingMode(MiscReg Stat) - { - if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) - return mode_kernel; - else{ - if((Stat & 0x18) == 0x8) - return mode_supervisor; - else if((Stat & 0x18) == 0x10) - return mode_user; - else return mode_number; - } - } - - // return a no-op instruction... used for instruction fetch faults const ExtMachInst NoopMachInst = 0x00000000; - // Constants Related to the number of registers - const int NumIntArchRegs = 32; - const int NumIntSpecialRegs = 9; - const int NumFloatArchRegs = 32; - const int NumFloatSpecialRegs = 5; - - const int MaxShadowRegSets = 16; // Maximum number of shadow register sets - const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs - const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// - - // Static instruction parameters - const int MaxInstSrcRegs = 10; - const int MaxInstDestRegs = 8; - - // semantically meaningful register indices - const int ZeroReg = 0; - const int AssemblerReg = 1; - const int SyscallSuccessReg = 7; - const int FirstArgumentReg = 4; - const int ReturnValueReg = 2; - - const int KernelReg0 = 26; - const int KernelReg1 = 27; - const int GlobalPointerReg = 28; - const int StackPointerReg = 29; - const int FramePointerReg = 30; - const int ReturnAddressReg = 31; - - const int SyscallPseudoReturnReg = 3; - const int LogVMPageSize = 13; // 8K bytes const int VMPageSize = (1 << LogVMPageSize); @@ -213,174 +168,6 @@ namespace MipsISA const int ANNOTE_NONE = 0; const uint32_t ITOUCH_ANNOTE = 0xffffffff; - - // These help enumerate all the registers for dependence tracking. - const int FP_Base_DepTag = NumIntRegs; - const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; - - // Enumerate names for 'Control' Registers in the CPU - // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 - // (Register Number-Register Select) Summary of Register - //------------------------------------------------------ - // The first set of names classify the CP0 names as Register Banks - // for easy indexing when using the 'RD + SEL' index combination - // in CP0 instructions. - enum MiscRegTags { - Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3 - MVPControl, - MVPConf0, - MVPConf1, - - CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15 - VPEControl, - VPEConf0, - VPEConf1, - YQMask, - VPESchedule, - VPEScheFBack, - VPEOpt, - - EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23 - TCStatus, - TCBind, - TCRestart, - TCHalt, - TCContext, - TCSchedule, - TCScheFBack, - - EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24 - - Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33 - ContextConfig, - - PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41 - PageGrain = Ctrl_Base_DepTag + 41, - - Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55 - SRSConf0, - SRSConf1, - SRSConf2, - SRSConf3, - SRSConf4, - - HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63 - - BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71 - - Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79 - - EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87 - - Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95 - - Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103 - IntCtl, - SRSCtl, - SRSMap, - - Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111 - - EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119 - - PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127, - EBase, - - Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135 - Config1, - Config2, - Config3, - Config4, - Config5, - Config6, - Config7, - - - LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143 - - WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151 - WatchLo1, - WatchLo2, - WatchLo3, - WatchLo4, - WatchLo5, - WatchLo6, - WatchLo7, - - WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159 - WatchHi1, - WatchHi2, - WatchHi3, - WatchHi4, - WatchHi5, - WatchHi6, - WatchHi7, - - XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167 - - //Bank 21: 168-175 - - //Bank 22: 176-183 - - Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191 - TraceControl1, - TraceControl2, - UserTraceData, - TraceBPC, - - DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199 - - PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207 - PerfCnt1, - PerfCnt2, - PerfCnt3, - PerfCnt4, - PerfCnt5, - PerfCnt6, - PerfCnt7, - - ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215 - - CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223 - CacheErr1, - CacheErr2, - CacheErr3, - - TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231 - DataLo1, - TagLo2, - DataLo3, - TagLo4, - DataLo5, - TagLo6, - DataLo7, - - TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239 - DataHi1, - TagHi2, - DataHi3, - TagHi4, - DataHi5, - TagHi6, - DataHi7, - - - ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247 - - DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256 - - LLFlag = Ctrl_Base_DepTag + 257, - - NumControlRegs - }; - - const int TotalDataRegs = NumIntRegs + NumFloatRegs; - - const int NumMiscRegs = NumControlRegs; - - const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; - - }; #endif // __ARCH_MIPS_ISA_TRAITS_HH__ diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh index 021b8cf73..e202a11aa 100644 --- a/src/arch/mips/locked_mem.hh +++ b/src/arch/mips/locked_mem.hh @@ -37,7 +37,7 @@ * ISA-specific helper functions for locked memory accesses. */ -#include "arch/isa_traits.hh" +#include "arch/registers.hh" #include "base/misc.hh" #include "base/trace.hh" #include "mem/request.hh" diff --git a/src/arch/mips/mips_core_specific.cc b/src/arch/mips/mips_core_specific.cc index 80d856b0c..21847378f 100755 --- a/src/arch/mips/mips_core_specific.cc +++ b/src/arch/mips/mips_core_specific.cc @@ -109,19 +109,4 @@ MipsISA::processInterrupts(CPU *cpu) */ } - -/*int -MipsISA::MiscRegFile::getInstAsid() -{ - return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); -} - -int -MipsISA::MiscRegFile::getDataAsid() -{ - return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); - }*/ - - - #endif // FULL_SYSTEM || BARE_IRON diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh index 8b4c9f908..b581d5cf0 100755 --- a/src/arch/mips/mt.hh +++ b/src/arch/mips/mt.hh @@ -37,9 +37,10 @@ * ISA-specific helper functions for multithreaded execution. */ -#include "arch/isa_traits.hh" #include "arch/mips/faults.hh" +#include "arch/mips/isa_traits.hh" #include "arch/mips/mt_constants.hh" +#include "arch/mips/registers.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "base/misc.hh" diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc deleted file mode 100644 index 908302866..000000000 --- a/src/arch/mips/regfile.cc +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - * Korey Sewell - */ - -#ifndef __ARCH_MIPS_REGFILE_REGFILE_HH__ -#define __ARCH_MIPS_REGFILE_REGFILE_HH__ - -#include "arch/mips/types.hh" -#include "arch/mips/isa_traits.hh" -#include "arch/mips/mt.hh" -#include "arch/mips/regfile/int_regfile.hh" -#include "arch/mips/regfile/float_regfile.hh" -#include "arch/mips/regfile/misc_regfile.hh" -#include "sim/faults.hh" - -class Checkpoint; -class ThreadContext; - -using namespace MipsISA; - -void RegFile::clear() -{ - intRegFile.clear(); - floatRegFile.clear(); - miscRegFile.clear(); -} - -void -RegFile::reset(std::string core_name, ThreadID num_threads, - unsigned num_vpes) -{ - bzero(&intRegFile, sizeof(intRegFile)); - bzero(&floatRegFile, sizeof(floatRegFile)); - miscRegFile.reset(core_name, num_threads, num_vpes); -} - -IntReg RegFile::readIntReg(int intReg) -{ - return intRegFile.readReg(intReg); -} - -Fault RegFile::setIntReg(int intReg, const IntReg &val) -{ - return intRegFile.setReg(intReg, val); -} - -MiscReg -RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid = 0) -{ - return miscRegFile.readRegNoEffect(miscReg, tid); -} - -MiscReg -RegFile::readMiscReg(int miscReg, ThreadContext *tc, ThreadID tid = 0) -{ - return miscRegFile.readReg(miscReg, tc, tid); -} - -void -RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, ThreadID tid = 0) -{ - miscRegFile.setRegNoEffect(miscReg, val, tid); -} - -void -RegFile::setMiscReg(int miscReg, const MiscReg &val, - ThreadContext *tc, ThreadID tid = 0) -{ - miscRegFile.setReg(miscReg, val, tc, tid); -} - -FloatRegVal RegFile::readFloatReg(int floatReg) -{ - return floatRegFile.readReg(floatReg,SingleWidth); -} - -FloatRegVal RegFile::readFloatReg(int floatReg, int width) -{ - return floatRegFile.readReg(floatReg,width); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg) -{ - return floatRegFile.readRegBits(floatReg,SingleWidth); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg, int width) -{ - return floatRegFile.readRegBits(floatReg,width); -} - -Fault RegFile::setFloatReg(int floatReg, const FloatRegVal &val) -{ - return floatRegFile.setReg(floatReg, val, SingleWidth); -} - -Fault RegFile::setFloatReg(int floatReg, const FloatRegVal &val, int width) -{ - return floatRegFile.setReg(floatReg, val, width); -} - -Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) -{ - return floatRegFile.setRegBits(floatReg, val, SingleWidth); -} - -Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) -{ - return floatRegFile.setRegBits(floatReg, val, width); -} - -Addr RegFile::readPC() -{ - return pc; -} - -void RegFile::setPC(Addr val) -{ - pc = val; -} - -Addr RegFile::readNextPC() -{ - return npc; -} - -void RegFile::setNextPC(Addr val) -{ - npc = val; -} - -Addr RegFile::readNextNPC() -{ - return nnpc; -} - -void RegFile::setNextNPC(Addr val) -{ - nnpc = val; -} - -void -RegFile::serialize(std::ostream &os) -{ - intRegFile.serialize(os); - floatRegFile.serialize(os); - miscRegFile.serialize(os); - - SERIALIZE_SCALAR(pc); - SERIALIZE_SCALAR(npc); - SERIALIZE_SCALAR(nnpc); -} - - -void -RegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - intRegFile.unserialize(cp, section); - floatRegFile.unserialize(cp, section); - miscRegFile.unserialize(cp, section); - UNSERIALIZE_SCALAR(pc); - UNSERIALIZE_SCALAR(npc); - UNSERIALIZE_SCALAR(nnpc); - -} - -static inline int flattenIntIndex(ThreadContext * tc, int reg) -{ - return reg; -} - -void -MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Regs Not Implemented Yet\n"); -} - -void -MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Misc. Regs Not Implemented Yet\n"); -} diff --git a/src/arch/mips/regfile.hh b/src/arch/mips/regfile.hh deleted file mode 100644 index 29586a652..000000000 --- a/src/arch/mips/regfile.hh +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __ARCH_MIPS_REGFILE_HH__ -#define __ARCH_MIPS_REGFILE_HH__ - -#include "arch/mips/regfile/regfile.hh" - -#endif diff --git a/src/arch/mips/regfile/float_regfile.cc b/src/arch/mips/regfile/float_regfile.cc deleted file mode 100644 index 2b32bd3af..000000000 --- a/src/arch/mips/regfile/float_regfile.cc +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Korey Sewell - */ - -#include "arch/mips/regfile/float_regfile.hh" -#include "sim/serialize.hh" - -using namespace MipsISA; -using namespace std; - -void -FloatRegFile::clear() -{ - bzero(®s, sizeof(regs)); -} - -double -FloatRegFile::readReg(int floatReg, int width, ThreadID tid) -{ - switch(width) - { - case SingleWidth: - { - void *float_ptr = ®s[floatReg]; - return *(float *) float_ptr; - } - - case DoubleWidth: - { - uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg]; - void *double_ptr = &double_val; - return *(double *) double_ptr; - } - - default: - panic("Attempted to read a %d bit floating point register!", width); - } -} - -FloatRegBits -FloatRegFile::readRegBits(int floatReg, int width, ThreadID tid) -{ - if (floatReg < NumFloatArchRegs - 1) { - switch(width) - { - case SingleWidth: - return regs[floatReg]; - - case DoubleWidth: - return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg]; - - default: - panic("Attempted to read a %d bit floating point register!", width); - } - } else { - if (width > SingleWidth) - assert("Control Regs are only 32 bits wide"); - - return regs[floatReg]; - } -} - -Fault -FloatRegFile::setReg(int floatReg, const FloatRegVal &val, int width, - ThreadID tid) -{ - switch(width) - { - case SingleWidth: - { - float temp = val; - void *float_ptr = &temp; - regs[floatReg] = *(FloatReg32 *) float_ptr; - break; - } - - case DoubleWidth: - { - const void *double_ptr = &val; - FloatReg64 temp_double = *(FloatReg64 *) double_ptr; - regs[floatReg + 1] = bits(temp_double, 63, 32); - regs[floatReg] = bits(temp_double, 31, 0); - break; - } - - default: - panic("Attempted to read a %d bit floating point register!", width); - } - - return NoFault; -} - -Fault -FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width, - ThreadID tid) -{ - switch(width) - { - case SingleWidth: - regs[floatReg] = val; - break; - - case DoubleWidth: - regs[floatReg + 1] = bits(val, 63, 32); - regs[floatReg] = bits(val, 31, 0); - break; - - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return NoFault; -} - -void -FloatRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(regs, NumFloatRegs); -} - -void -FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(regs, NumFloatRegs); -} diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh deleted file mode 100644 index afe6701c5..000000000 --- a/src/arch/mips/regfile/float_regfile.hh +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - */ - -#ifndef __ARCH_MIPS_REGFILE_FLOAT_REGFILE_HH__ -#define __ARCH_MIPS_REGFILE_FLOAT_REGFILE_HH__ - -#include "arch/mips/types.hh" -#include "arch/mips/isa_traits.hh" -#include "base/misc.hh" -#include "base/bitfield.hh" -#include "sim/faults.hh" - -#include <string> - -class Checkpoint; - -namespace MipsISA -{ - const uint32_t MIPS32_QNAN = 0x7fbfffff; - const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff); - - enum FPControlRegNums { - FIR = NumFloatArchRegs, - FCCR, - FEXR, - FENR, - FCSR - }; - - enum FCSRBits { - Inexact = 1, - Underflow, - Overflow, - DivideByZero, - Invalid, - Unimplemented - }; - - enum FCSRFields { - Flag_Field = 1, - Enable_Field = 6, - Cause_Field = 11 - }; - - const int SingleWidth = 32; - const int SingleBytes = SingleWidth / 4; - - const int DoubleWidth = 64; - const int DoubleBytes = DoubleWidth / 4; - - const int QuadWidth = 128; - const int QuadBytes = QuadWidth / 4; - - class FloatRegFile - { - protected: - FloatReg32 regs[NumFloatRegs]; - - public: - static const int regWidth = SingleWidth; - - void clear(); - double readReg(int floatReg, int width, ThreadID tid = 0); - FloatRegBits readRegBits(int floatReg, int width, ThreadID tid = 0); - Fault setReg(int floatReg, const FloatRegVal &val, int width, - ThreadID tid = 0); - Fault setRegBits(int floatReg, const FloatRegBits &val, int width, - ThreadID tid = 0); - - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); - }; - -} // namespace MipsISA - -#endif diff --git a/src/arch/mips/regfile/int_regfile.cc b/src/arch/mips/regfile/int_regfile.cc deleted file mode 100644 index 88de4be94..000000000 --- a/src/arch/mips/regfile/int_regfile.cc +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Korey Sewell - * Jaidev Patwardhan - */ - -#include "arch/mips/regfile/int_regfile.hh" -#include "sim/serialize.hh" - -using namespace MipsISA; -using namespace std; - -void -IntRegFile::clear() -{ - bzero(®s, sizeof(regs)); - currShadowSet=0; -} - -int -IntRegFile::readShadowSet() -{ - return currShadowSet; -} - -void -IntRegFile::setShadowSet(int css) -{ - DPRINTF(MipsPRA, "Setting Shadow Set to :%d (%s)\n", css, currShadowSet); - currShadowSet = css; -} - -IntReg -IntRegFile::readReg(int intReg) -{ - if (intReg < NumIntArchRegs) { - // Regular GPR Read - DPRINTF(MipsPRA, "Reading Reg: %d, CurrShadowSet: %d\n", intReg, - currShadowSet); - - return regs[intReg + NumIntArchRegs * currShadowSet]; - } else { - unsigned special_reg_num = intReg - NumIntArchRegs; - - // Read A Special Reg - return regs[TotalArchRegs + special_reg_num]; - } -} - -Fault -IntRegFile::setReg(int intReg, const IntReg &val) -{ - if (intReg != ZeroReg) { - if (intReg < NumIntArchRegs) { - regs[intReg + NumIntArchRegs * currShadowSet] = val; - } else { - unsigned special_reg_num = intReg - NumIntArchRegs; - - regs[TotalArchRegs + special_reg_num] = val; - } - } - - return NoFault; -} - -void -IntRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(regs, NumIntRegs); -} - -void -IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(regs, NumIntRegs); -} diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh deleted file mode 100644 index 3c7c8c64c..000000000 --- a/src/arch/mips/regfile/int_regfile.hh +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - */ - -#ifndef __ARCH_MIPS_REGFILE_INT_REGFILE_HH__ -#define __ARCH_MIPS_REGFILE_INT_REGFILE_HH__ - -#include "arch/mips/types.hh" -#include "arch/mips/isa_traits.hh" -#include "base/misc.hh" -#include "base/trace.hh" -#include "sim/faults.hh" - -class Checkpoint; - -namespace MipsISA -{ - enum MiscIntRegNums { - LO = NumIntArchRegs, - HI, - DSPACX0, - DSPLo1, - DSPHi1, - DSPACX1, - DSPLo2, - DSPHi2, - DSPACX2, - DSPLo3, - DSPHi3, - DSPACX3, - DSPControl, - DSPLo0 = LO, - DSPHi0 = HI - }; - - //@TODO: Implementing ShadowSets needs to - //edit this value such that: - //TotalArchRegs = NumIntArchRegs * ShadowSets - const int TotalArchRegs = NumIntArchRegs; - - class IntRegFile - { - protected: - IntReg regs[NumIntRegs]; - int currShadowSet; - public: - void clear(); - int readShadowSet(); - void setShadowSet(int css); - IntReg readReg(int intReg); - Fault setReg(int intReg, const IntReg &val); - - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); - - }; - -} // namespace MipsISA - -#endif diff --git a/src/arch/mips/regfile/regfile.cc b/src/arch/mips/regfile/regfile.cc deleted file mode 100644 index 975fad963..000000000 --- a/src/arch/mips/regfile/regfile.cc +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Korey Sewell - */ - -#include "arch/mips/regfile/regfile.hh" -#include "sim/serialize.hh" - -using namespace std; - -namespace MipsISA -{ - -void -RegFile::clear() -{ - intRegFile.clear(); - floatRegFile.clear(); - miscRegFile.clear(); -} - -void -RegFile::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes, - BaseCPU *_cpu) -{ - bzero(&intRegFile, sizeof(intRegFile)); - bzero(&floatRegFile, sizeof(floatRegFile)); - miscRegFile.reset(core_name, num_threads, num_vpes, _cpu); -} - -IntReg -RegFile::readIntReg(int intReg) -{ - return intRegFile.readReg(intReg); -} - -Fault -RegFile::setIntReg(int intReg, const IntReg &val) -{ - return intRegFile.setReg(intReg, val); -} - -MiscReg -RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid) -{ - return miscRegFile.readRegNoEffect(miscReg, tid); -} - -MiscReg -RegFile::readMiscReg(int miscReg, ThreadContext *tc, ThreadID tid) -{ - return miscRegFile.readReg(miscReg, tc, tid); -} - -void -RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, ThreadID tid) -{ - miscRegFile.setRegNoEffect(miscReg, val, tid); -} - -void -RegFile::setMiscReg(int miscReg, const MiscReg &val, - ThreadContext *tc, ThreadID tid) -{ - miscRegFile.setReg(miscReg, val, tc, tid); -} - -FloatRegVal -RegFile::readFloatReg(int floatReg) -{ - return floatRegFile.readReg(floatReg,SingleWidth); -} - -FloatRegVal -RegFile::readFloatReg(int floatReg, int width) -{ - return floatRegFile.readReg(floatReg,width); -} - -FloatRegBits -RegFile::readFloatRegBits(int floatReg) -{ - return floatRegFile.readRegBits(floatReg,SingleWidth); -} - -FloatRegBits -RegFile::readFloatRegBits(int floatReg, int width) -{ - return floatRegFile.readRegBits(floatReg,width); -} - -Fault -RegFile::setFloatReg(int floatReg, const FloatRegVal &val) -{ - return floatRegFile.setReg(floatReg, val, SingleWidth); -} - -Fault -RegFile::setFloatReg(int floatReg, const FloatRegVal &val, int width) -{ - return floatRegFile.setReg(floatReg, val, width); -} - -Fault -RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) -{ - return floatRegFile.setRegBits(floatReg, val, SingleWidth); -} - -Fault -RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) -{ - return floatRegFile.setRegBits(floatReg, val, width); -} - -void -RegFile::setShadowSet(int css){ - intRegFile.setShadowSet(css); -} - -int -RegFile::instAsid() -{ - return miscRegFile.getInstAsid(); -} - -int -RegFile::dataAsid() -{ - return miscRegFile.getDataAsid(); -} - -Addr -RegFile::readPC() -{ - return pc; -} - -void -RegFile::setPC(Addr val) -{ - pc = val; -} - -Addr -RegFile::readNextPC() -{ - return npc; -} - -void -RegFile::setNextPC(Addr val) -{ - npc = val; -} - -Addr -RegFile::readNextNPC() -{ - return nnpc; -} - -void -RegFile::setNextNPC(Addr val) -{ - nnpc = val; -} - -void -RegFile::serialize(EventManager *em, std::ostream &os) -{ - intRegFile.serialize(os); - //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs); - //SERIALZE_ARRAY(miscRegFile); - //SERIALIZE_SCALAR(miscRegs.fpcr); - //SERIALIZE_SCALAR(miscRegs.lock_flag); - //SERIALIZE_SCALAR(miscRegs.lock_addr); - SERIALIZE_SCALAR(pc); - SERIALIZE_SCALAR(npc); - SERIALIZE_SCALAR(nnpc); -} - -void -RegFile::unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion) -{ - intRegFile.unserialize(cp, section); - //UNSERIALIZE_ARRAY(floatRegFile); - //UNSERIALZE_ARRAY(miscRegFile); - //UNSERIALIZE_SCALAR(miscRegs.fpcr); - //UNSERIALIZE_SCALAR(miscRegs.lock_flag); - //UNSERIALIZE_SCALAR(miscRegs.lock_addr); - UNSERIALIZE_SCALAR(pc); - UNSERIALIZE_SCALAR(npc); - UNSERIALIZE_SCALAR(nnpc); - -} - -} // namespace MipsISA diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh deleted file mode 100644 index 91951b078..000000000 --- a/src/arch/mips/regfile/regfile.hh +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - */ - -#ifndef __ARCH_MIPS_REGFILE_REGFILE_HH__ -#define __ARCH_MIPS_REGFILE_REGFILE_HH__ - -#include "arch/mips/types.hh" -#include "arch/mips/isa_traits.hh" -//#include "arch/mips/mt.hh" -#include "arch/mips/regfile/int_regfile.hh" -#include "arch/mips/regfile/float_regfile.hh" -#include "arch/mips/regfile/misc_regfile.hh" -//#include "cpu/base.hh" -#include "sim/faults.hh" - -class BaseCPU; -class Checkpoint; -class EventManager; - -namespace MipsISA -{ - class RegFile { - protected: - Addr pc; // program counter - Addr npc; // next-cycle program counter - Addr nnpc; // next-next-cycle program counter - // used to implement branch delay slot - // not real register - - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegFile; // control register file - - public: - void clear(); - void reset(std::string core_name, ThreadID num_threads, - unsigned num_vpes, BaseCPU *_cpu); - MiscRegFile *getMiscRegFilePtr(); - - IntReg readIntReg(int intReg); - Fault setIntReg(int intReg, const IntReg &val); - - - MiscReg readMiscRegNoEffect(int miscReg, ThreadID tid = 0); - MiscReg readMiscReg(int miscReg, ThreadContext *tc, - ThreadID tid = 0); - void setMiscRegNoEffect(int miscReg, const MiscReg &val, - ThreadID tid = 0); - void setMiscReg(int miscReg, const MiscReg &val, - ThreadContext *tc, ThreadID tid = 0); - - FloatRegVal readFloatReg(int floatReg); - FloatRegVal readFloatReg(int floatReg, int width); - FloatRegBits readFloatRegBits(int floatReg); - FloatRegBits readFloatRegBits(int floatReg, int width); - Fault setFloatReg(int floatReg, const FloatRegVal &val); - Fault setFloatReg(int floatReg, const FloatRegVal &val, int width); - Fault setFloatRegBits(int floatReg, const FloatRegBits &val); - Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width); - - - void setShadowSet(int css); - - int instAsid(); - int dataAsid(); - - public: - Addr readPC(); - void setPC(Addr val); - - Addr readNextPC(); - void setNextPC(Addr val); - - Addr readNextNPC(); - void setNextNPC(Addr val); - - void serialize(EventManager *em, std::ostream &os); - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion); - - }; - -} // namespace MipsISA - -#endif diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh new file mode 100644 index 000000000..b996b4717 --- /dev/null +++ b/src/arch/mips/registers.hh @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * Copyright (c) 2007 MIPS Technologies, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Korey Sewell + */ + +#ifndef __ARCH_MIPS_REGISTERS_HH__ +#define __ARCH_MIPS_REGISTERS_HH__ + +#include "arch/mips/max_inst_regs.hh" +#include "base/misc.hh" +#include "base/types.hh" + +class ThreadContext; + +namespace MipsISA +{ + +using MipsISAInst::MaxInstSrcRegs; +using MipsISAInst::MaxInstDestRegs; + +// Constants Related to the number of registers +const int NumIntArchRegs = 32; +const int NumIntSpecialRegs = 9; +const int NumFloatArchRegs = 32; +const int NumFloatSpecialRegs = 5; + +const int MaxShadowRegSets = 16; // Maximum number of shadow register sets +const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs +const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// + +const uint32_t MIPS32_QNAN = 0x7fbfffff; +const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff); + +enum FPControlRegNums { + FIR = NumFloatArchRegs, + FCCR, + FEXR, + FENR, + FCSR +}; + +enum FCSRBits { + Inexact = 1, + Underflow, + Overflow, + DivideByZero, + Invalid, + Unimplemented +}; + +enum FCSRFields { + Flag_Field = 1, + Enable_Field = 6, + Cause_Field = 11 +}; + +enum MiscIntRegNums { + LO = NumIntArchRegs, + HI, + DSPACX0, + DSPLo1, + DSPHi1, + DSPACX1, + DSPLo2, + DSPHi2, + DSPACX2, + DSPLo3, + DSPHi3, + DSPACX3, + DSPControl, + DSPLo0 = LO, + DSPHi0 = HI +}; + +// semantically meaningful register indices +const int ZeroReg = 0; +const int AssemblerReg = 1; +const int SyscallSuccessReg = 7; +const int FirstArgumentReg = 4; +const int ReturnValueReg = 2; + +const int KernelReg0 = 26; +const int KernelReg1 = 27; +const int GlobalPointerReg = 28; +const int StackPointerReg = 29; +const int FramePointerReg = 30; +const int ReturnAddressReg = 31; + +const int SyscallPseudoReturnReg = 3; + +//@TODO: Implementing ShadowSets needs to +//edit this value such that: +//TotalArchRegs = NumIntArchRegs * ShadowSets +const int TotalArchRegs = NumIntArchRegs; + +// These help enumerate all the registers for dependence tracking. +const int FP_Base_DepTag = NumIntRegs; +const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; + +// Enumerate names for 'Control' Registers in the CPU +// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 +// (Register Number-Register Select) Summary of Register +//------------------------------------------------------ +// The first set of names classify the CP0 names as Register Banks +// for easy indexing when using the 'RD + SEL' index combination +// in CP0 instructions. +enum MiscRegTags { + Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3 + MVPControl, + MVPConf0, + MVPConf1, + + CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15 + VPEControl, + VPEConf0, + VPEConf1, + YQMask, + VPESchedule, + VPEScheFBack, + VPEOpt, + + EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23 + TCStatus, + TCBind, + TCRestart, + TCHalt, + TCContext, + TCSchedule, + TCScheFBack, + + EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24 + + Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33 + ContextConfig, + + PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41 + PageGrain = Ctrl_Base_DepTag + 41, + + Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55 + SRSConf0, + SRSConf1, + SRSConf2, + SRSConf3, + SRSConf4, + + HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63 + + BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71 + + Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79 + + EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87 + + Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95 + + Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103 + IntCtl, + SRSCtl, + SRSMap, + + Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111 + + EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119 + + PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127, + EBase, + + Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135 + Config1, + Config2, + Config3, + Config4, + Config5, + Config6, + Config7, + + + LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143 + + WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151 + WatchLo1, + WatchLo2, + WatchLo3, + WatchLo4, + WatchLo5, + WatchLo6, + WatchLo7, + + WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159 + WatchHi1, + WatchHi2, + WatchHi3, + WatchHi4, + WatchHi5, + WatchHi6, + WatchHi7, + + XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167 + + //Bank 21: 168-175 + + //Bank 22: 176-183 + + Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191 + TraceControl1, + TraceControl2, + UserTraceData, + TraceBPC, + + DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199 + + PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207 + PerfCnt1, + PerfCnt2, + PerfCnt3, + PerfCnt4, + PerfCnt5, + PerfCnt6, + PerfCnt7, + + ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215 + + CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223 + CacheErr1, + CacheErr2, + CacheErr3, + + TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231 + DataLo1, + TagLo2, + DataLo3, + TagLo4, + DataLo5, + TagLo6, + DataLo7, + + TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239 + DataHi1, + TagHi2, + DataHi3, + TagHi4, + DataHi5, + TagHi6, + DataHi7, + + + ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247 + + DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256 + + LLFlag = Ctrl_Base_DepTag + 257, + + NumControlRegs +}; + +const int TotalDataRegs = NumIntRegs + NumFloatRegs; + +const int NumMiscRegs = NumControlRegs; + +const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; + +typedef uint16_t RegIndex; + +typedef uint32_t IntReg; + +// floating point register file entry type +typedef uint32_t FloatRegBits; +typedef float FloatReg; + +// cop-0/cop-1 system control register +typedef uint64_t MiscReg; + +typedef union { + IntReg intreg; + FloatReg fpreg; + MiscReg ctrlreg; +} AnyReg; + +} // namespace MipsISA + +#endif diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index 001dc2cb7..18a29122c 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -58,6 +58,21 @@ using namespace MipsISA; #define MODE2MASK(X) (1 << (X)) +static inline mode_type +getOperatingMode(MiscReg Stat) +{ + if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) { + return mode_kernel; + } else if((Stat & 0x18) == 0x8) { + return mode_supervisor; + } else if((Stat & 0x18) == 0x10) { + return mode_user; + } else { + return mode_number; + } +} + + TLB::TLB(const Params *p) : BaseTLB(p), size(p->size), nlu(0) { diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh index 4e0684e78..f203d7d57 100644 --- a/src/arch/mips/types.hh +++ b/src/arch/mips/types.hh @@ -37,29 +37,9 @@ namespace MipsISA { typedef uint32_t MachInst; typedef uint64_t ExtMachInst; - typedef uint16_t RegIndex; - typedef uint32_t IntReg; typedef uint64_t LargestRead; - - // floating point register file entry type - typedef uint32_t FloatReg32; - typedef uint64_t FloatReg64; - typedef uint64_t FloatRegBits; - - typedef double FloatRegVal; - typedef double FloatReg; - - // cop-0/cop-1 system control register - typedef uint64_t MiscReg; - - typedef union { - IntReg intreg; - FloatReg fpreg; - MiscReg ctrlreg; - } AnyReg; - //used in FP convert & round function enum ConvertType{ SINGLE_TO_DOUBLE, diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index 5908caf68..4723d6301 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -233,18 +233,6 @@ isSnan(void *val_ptr, int size) } } -void -copyRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Regs Not Implemented Yet\n"); -} - -void -copyMiscRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Misc. Regs Not Implemented Yet\n"); -} - template <class CPU> void zeroRegisters(CPU *cpu) @@ -262,4 +250,16 @@ startupCPU(ThreadContext *tc, int cpuId) tc->activate(0/*tc->threadId()*/); } +void +copyRegs(ThreadContext *src, ThreadContext *dest) +{ + panic("Copy Regs Not Implemented Yet\n"); +} + +void +copyMiscRegs(ThreadContext *src, ThreadContext *dest) +{ + panic("Copy Misc. Regs Not Implemented Yet\n"); +} + } // namespace MipsISA diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index 1c77b6ff2..23c965bd4 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -98,27 +98,11 @@ namespace MipsISA { // // Register File Utility Functions // - static inline int flattenFloatIndex(ThreadContext * tc, int reg) - { - return reg; - } - - static inline int flattenIntIndex(ThreadContext * tc, int reg) - { - // Implement Shadow Sets Stuff Here; - return reg; - } - static inline MachInst makeRegisterCopy(int dest, int src) { panic("makeRegisterCopy not implemented"); return 0; } - void copyRegs(ThreadContext *src, ThreadContext *dest); - - void copyMiscRegs(ThreadContext *src, ThreadContext *dest); - - template <class CPU> void zeroRegisters(CPU *cpu); @@ -139,6 +123,9 @@ namespace MipsISA { // CPU Utility // void startupCPU(ThreadContext *tc, int cpuId); + + void copyRegs(ThreadContext *src, ThreadContext *dest); + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); }; |