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-rw-r--r--src/arch/mips/faults.cc1
-rw-r--r--src/arch/mips/isa.cc1
-rw-r--r--src/arch/mips/isa/includes.isa1
-rw-r--r--src/arch/mips/linux/process.cc1
-rw-r--r--src/arch/mips/locked_mem.hh1
-rw-r--r--src/arch/mips/process.cc1
-rw-r--r--src/arch/mips/stacktrace.hh1
-rw-r--r--src/arch/mips/tlb.cc2
8 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 9bb945dba..652b5960c 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -36,6 +36,7 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/MipsPRA.hh"
#if !FULL_SYSTEM
#include "mem/page_table.hh"
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 902574bac..6a525ed3a 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -35,6 +35,7 @@
#include "base/bitfield.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/MipsPRA.hh"
namespace MipsISA
{
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index b0d1aa748..73d751f6e 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -82,6 +82,7 @@ output exec {{
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
+#include "debug/MipsPRA.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/eventq.hh"
diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc
index fa8e659b6..156d4ea05 100644
--- a/src/arch/mips/linux/process.cc
+++ b/src/arch/mips/linux/process.cc
@@ -35,6 +35,7 @@
#include "arch/mips/isa_traits.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/SyscallVerbose.hh"
#include "kern/linux/linux.hh"
#include "sim/eventq.hh"
#include "sim/process.hh"
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 1cc08ee3d..60df8252a 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -40,6 +40,7 @@
#include "arch/registers.hh"
#include "base/misc.hh"
#include "base/trace.hh"
+#include "debug/LLSC.hh"
#include "mem/request.hh"
namespace MipsISA
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index b6f21c95c..c62b60b98 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -36,6 +36,7 @@
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
+#include "debug/Loader.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/process_impl.hh"
diff --git a/src/arch/mips/stacktrace.hh b/src/arch/mips/stacktrace.hh
index 4c02cc86c..8520c3d1b 100644
--- a/src/arch/mips/stacktrace.hh
+++ b/src/arch/mips/stacktrace.hh
@@ -33,6 +33,7 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "debug/Stack.hh"
class ThreadContext;
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index b73eae72f..0f76363c8 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -43,6 +43,8 @@
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/MipsPRA.hh"
+#include "debug/TLB.hh"
#include "mem/page_table.hh"
#include "params/MipsTLB.hh"
#include "sim/process.hh"