diff options
Diffstat (limited to 'src/arch/mips')
-rw-r--r-- | src/arch/mips/isa.cc | 10 | ||||
-rw-r--r-- | src/arch/mips/isa.hh | 4 | ||||
-rw-r--r-- | src/arch/mips/mmapped_ipr.hh | 4 | ||||
-rwxr-xr-x | src/arch/mips/mt.hh | 2 | ||||
-rw-r--r-- | src/arch/mips/utility.cc | 2 |
5 files changed, 11 insertions, 11 deletions
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc index 6a525ed3a..f6de102cd 100644 --- a/src/arch/mips/isa.cc +++ b/src/arch/mips/isa.cc @@ -482,7 +482,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, miscRegFile[misc_reg][reg_sel] = cp0_val; - scheduleCP0Update(tc->getCpuPtr(), 1); + scheduleCP0Update(tc->getCpuPtr(), Cycles(1)); } /** @@ -511,14 +511,14 @@ ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) } void -ISA::scheduleCP0Update(BaseCPU *cpu, int delay) +ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay) { if (!cp0Updated) { cp0Updated = true; //schedule UPDATE CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0); - cpu->schedule(cp0_event, curTick() + cpu->ticks(delay)); + cpu->schedule(cp0_event, cpu->clockEdge(delay)); } } @@ -573,9 +573,9 @@ ISA::CP0Event::description() const } void -ISA::CP0Event::scheduleEvent(int delay) +ISA::CP0Event::scheduleEvent(Cycles delay) { - cpu->reschedule(this, curTick() + cpu->ticks(delay), true); + cpu->reschedule(this, cpu->clockEdge(delay), true); } void diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh index 720c7725e..a313b4382 100644 --- a/src/arch/mips/isa.hh +++ b/src/arch/mips/isa.hh @@ -136,14 +136,14 @@ namespace MipsISA const char *description() const; /** Schedule This Event */ - void scheduleEvent(int delay); + void scheduleEvent(Cycles delay); /** Unschedule This Event */ void unscheduleEvent(); }; // Schedule a CP0 Update Event - void scheduleCP0Update(BaseCPU *cpu, int delay = 0); + void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0)); // If any changes have been made, then check the state for changes // and if necessary alert the CPU diff --git a/src/arch/mips/mmapped_ipr.hh b/src/arch/mips/mmapped_ipr.hh index 14d6e3f42..4c84d05f2 100644 --- a/src/arch/mips/mmapped_ipr.hh +++ b/src/arch/mips/mmapped_ipr.hh @@ -45,13 +45,13 @@ class ThreadContext; namespace MipsISA { -inline Tick +inline Cycles handleIprRead(ThreadContext *xc, Packet *pkt) { panic("No implementation for handleIprRead in MIPS\n"); } -inline Tick +inline Cycles handleIprWrite(ThreadContext *xc, Packet *pkt) { panic("No implementation for handleIprWrite in MIPS\n"); diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh index f163d3240..02e98a170 100755 --- a/src/arch/mips/mt.hh +++ b/src/arch/mips/mt.hh @@ -96,7 +96,7 @@ restoreThread(TC *tc) // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY tc->pcState(restartPC); - tc->activate(0); + tc->activate(Cycles(0)); warn("%i: Restoring thread %i in %s @ PC %x", curTick(), tc->threadId(), tc->getCpuPtr()->name(), restartPC); diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index 65432b4ea..f84819756 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -231,7 +231,7 @@ zeroRegisters(CPU *cpu) void startupCPU(ThreadContext *tc, int cpuId) { - tc->activate(0/*tc->threadId()*/); + tc->activate(Cycles(0)); } void |