3 files changed, 19 insertions, 11 deletions

diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 9ec93f3fe..00471aece 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -29,6 +29,8 @@
  * Authors: Gabe Black
  *          Korey Sewell
  *          Jaidev Patwardhan
+ *          Zhengxing Li
+ *          Deyuan Guo
  */
 
 #include "arch/mips/faults.hh"
@@ -121,7 +123,7 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
     DPRINTF(MipsPRA, "PC: %s\n", pc);
     bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
     tc->setMiscRegNoEffect(MISCREG_EPC,
-            pc.pc() - delay_slot ? sizeof(MachInst) : 0);
+            pc.pc() - (delay_slot ? sizeof(MachInst) : 0));
 
     // Set Cause_EXCCODE field
     CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 89b6924c6..76d4fff23 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -29,6 +29,8 @@
  * Authors: Gabe Black
  *          Korey Sewell
  *          Jaidev Patwardhan
+ *          Zhengxing Li
+ *          Deyuan Guo
  */
 
 #ifndef __MIPS_FAULTS_HH__
@@ -87,7 +89,7 @@ class MipsFaultBase : public FaultBase
     virtual FaultVect base(ThreadContext *tc) const
     {
         StatusReg status = tc->readMiscReg(MISCREG_STATUS);
-        if (status.bev)
+        if (!status.bev)
             return tc->readMiscReg(MISCREG_EBASE);
         else
             return 0xbfc00200;
@@ -166,7 +168,7 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
         if (FULL_SYSTEM) {
             CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
             cause.ce = coProcID;
-            tc->setMiscReg(MISCREG_CAUSE, cause);
+            tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
         }
     }
 };
@@ -178,7 +180,8 @@ class InterruptFault : public MipsFault<InterruptFault>
     offset(ThreadContext *tc) const
     {
         CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
-        return cause.iv ? 0x200 : 0x000;
+        // offset 0x200 for release 2, 0x180 for release 1.
+        return cause.iv ? 0x200 : 0x180;
     }
 };
 
@@ -250,9 +253,10 @@ class TlbFault : public AddressFault<T>
             StaticInstPtr inst = StaticInst::nullStaticInstPtr)
     {
         if (FULL_SYSTEM) {
-            DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
-            tc->pcState(this->vect(tc));
+            DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
+            Addr vect = this->vect(tc);
             setTlbExceptionState(tc, this->code());
+            tc->pcState(vect);
         } else {
             AddressFault<T>::invoke(tc, inst);
         }
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 57d8849e1..b3ed09621 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -29,6 +29,8 @@
  * Authors: Nathan Binkert
  *          Steve Reinhardt
  *          Jaidev Patwardhan
+ *          Zhengxing Li
+ *          Deyuan Guo
  */
 
 #include <string>
@@ -350,7 +352,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
           }
 
           if (Valid == false) {
-              return new InvalidFault(Asid, vaddr, vpn, false);
+              return new TlbInvalidFault(Asid, vaddr, VPN, false);
           } else {
               // Ok, this is really a match, set paddr
               Addr PAddr;
@@ -366,7 +368,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
             }
         } else {
             // Didn't find any match, return a TLB Refill Exception
-            return new RefillFault(Asid, vaddr, vpn, false);
+            return new TlbRefillFault(Asid, vaddr, VPN, false);
         }
     }
     return checkCacheability(req);
@@ -445,10 +447,10 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
             }
 
             if (Valid == false) {
-                return new InvalidFault(Asid, vaddr, VPN, true);
+                return new TlbInvalidFault(Asid, vaddr, VPN, write);
             } else {
                 // Ok, this is really a match, set paddr
-                if (!Dirty) {
+                if (!Dirty && write) {
                     return new TlbModifiedFault(Asid, vaddr, VPN);
                 }
                 Addr PAddr;
@@ -464,7 +466,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
             }
         } else {
             // Didn't find any match, return a TLB Refill Exception
-            return new RefillFault(Asid, vaddr, VPN, true);
+            return new TlbRefillFault(Asid, vaddr, VPN, write);
         }
     }
     return checkCacheability(req);