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-rw-r--r--src/arch/mips/isa/decoder.isa39
-rw-r--r--src/arch/mips/isa/formats/basic.isa2
-rw-r--r--src/arch/mips/isa/formats/branch.isa4
-rw-r--r--src/arch/mips/isa/formats/control.isa6
-rw-r--r--src/arch/mips/isa/formats/fp.isa12
-rw-r--r--src/arch/mips/isa/formats/int.isa15
-rw-r--r--src/arch/mips/isa/formats/mem.isa20
-rw-r--r--src/arch/mips/isa/formats/mt.isa2
-rw-r--r--src/arch/mips/isa/formats/noop.isa2
-rw-r--r--src/arch/mips/isa/formats/tlbop.isa4
-rw-r--r--src/arch/mips/isa/formats/trap.isa2
-rw-r--r--src/arch/mips/isa/formats/util.isa74
-rw-r--r--src/arch/mips/regfile/regfile.hh5
-rw-r--r--src/arch/mips/remote_gdb.hh64
-rw-r--r--src/arch/mips/syscallreturn.hh45
15 files changed, 151 insertions, 145 deletions
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index d65e3eb94..12f36c449 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -154,19 +154,20 @@ decode OPCODE_HI default Unknown::unknown() {
0x3: decode FUNCTION_LO {
format HiLoOp {
- 0x0: mult({{ val = Rs.sd * Rt.sd; }});
- 0x1: multu({{ val = Rs.ud * Rt.ud; }});
- }
-
- format HiLoMiscOp {
- 0x2: div({{ if (Rt.sd != 0) {
- HI = Rs.sd % Rt.sd;
- LO = Rs.sd / Rt.sd;
+ 0x0: mult({{ int64_t val = Rs.sd * Rt.sd; }});
+ 0x1: multu({{ uint64_t val = Rs.ud * Rt.ud; }});
+ 0x2: div({{ int64_t val;
+ if (Rt.sd != 0) {
+ int64_t hi = Rs.sd % Rt.sd;
+ int64_t lo = Rs.sd / Rt.sd;
+ val = (hi << 32) | lo;
}
}});
- 0x3: divu({{ if (Rt.ud != 0) {
- HI = Rs.ud % Rt.ud;
- LO = Rs.ud / Rt.ud;
+ 0x3: divu({{ uint64_t val;
+ if (Rt.ud != 0) {
+ uint64_t hi = Rs.ud % Rt.ud;
+ uint64_t lo = Rs.ud / Rt.ud;
+ val = (hi << 32) | lo;
}
}});
}
@@ -950,17 +951,17 @@ decode OPCODE_HI default Unknown::unknown() {
}});
format HiLoOp {
- 0x0: madd({{ val = ((int64_t) HI << 32 | LO) +
- (Rs.sd * Rt.sd);
+ 0x0: madd({{ int64_t val = ((int64_t) HI << 32 | LO) +
+ (Rs.sd * Rt.sd);
}});
- 0x1: maddu({{ val = ((uint64_t) HI << 32 | LO) +
- (Rs.ud * Rt.ud);
+ 0x1: maddu({{ uint64_t val = ((uint64_t) HI << 32 | LO) +
+ (Rs.ud * Rt.ud);
}});
- 0x4: msub({{ val = ((int64_t) HI << 32 | LO) -
- (Rs.sd * Rt.sd);
+ 0x4: msub({{ int64_t val = ((int64_t) HI << 32 | LO) -
+ (Rs.sd * Rt.sd);
}});
- 0x5: msubu({{ val = ((uint64_t) HI << 32 | LO) -
- (Rs.ud * Rt.ud);
+ 0x5: msubu({{ uint64_t val = ((uint64_t) HI << 32 | LO) -
+ (Rs.ud * Rt.ud);
}});
}
}
diff --git a/src/arch/mips/isa/formats/basic.isa b/src/arch/mips/isa/formats/basic.isa
index 29a445b2c..ec065b865 100644
--- a/src/arch/mips/isa/formats/basic.isa
+++ b/src/arch/mips/isa/formats/basic.isa
@@ -88,7 +88,7 @@ def template BasicDecodeWithMnemonic {{
// The most basic instruction format...
def format BasicOp(code, *flags) {{
- iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+ iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 8c89fbfa2..a67f04dca 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -247,7 +247,7 @@ def format Branch(code,*opt_flags) {{
code += '} else {\n'
code += not_taken_code
- iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), inst_flags)
+ iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -266,7 +266,7 @@ def format Jump(code, *opt_flags) {{
else:
inst_flags += (x, )
- iop = InstObjParams(name, Name, 'Jump', CodeBlock(code), inst_flags)
+ iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 6c7d396f3..1c63a6e22 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -130,7 +130,7 @@ output decoder {{
}};
def format System(code, *flags) {{
- iop = InstObjParams(name, Name, 'Control', CodeBlock(code), flags)
+ iop = InstObjParams(name, Name, 'Control', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -138,7 +138,7 @@ def format System(code, *flags) {{
}};
def format CP0Control(code, *flags) {{
- iop = InstObjParams(name, Name, 'CP0Control', CodeBlock(code), flags)
+ iop = InstObjParams(name, Name, 'CP0Control', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -146,7 +146,7 @@ def format CP0Control(code, *flags) {{
}};
def format CP1Control(code, *flags) {{
- iop = InstObjParams(name, Name, 'CP1Control', CodeBlock(code), flags)
+ iop = InstObjParams(name, Name, 'CP1Control', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 153f3f949..ac6805cc7 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -209,7 +209,7 @@ def template FloatingPointExecute {{
// Primary format for float point operate instructions:
def format FloatOp(code, *flags) {{
- iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
+ iop = InstObjParams(name, Name, 'FPOp', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -248,7 +248,7 @@ def format FloatCompareOp(cond_code, *flags) {{
code += cond_code + '}'
code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
- iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
+ iop = InstObjParams(name, Name, 'FPCompareOp', code)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -299,7 +299,7 @@ def format FloatConvertOp(code, *flags) {{
else:
code += 'val); '
- iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code))
+ iop = InstObjParams(name, Name, 'FPOp', code)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -307,7 +307,7 @@ def format FloatConvertOp(code, *flags) {{
}};
def format FloatAccOp(code, *flags) {{
- iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
+ iop = InstObjParams(name, Name, 'FPOp', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -316,7 +316,7 @@ def format FloatAccOp(code, *flags) {{
// Primary format for float64 operate instructions:
def format Float64Op(code, *flags) {{
- iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+ iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -364,7 +364,7 @@ def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
code += cond_code2
code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
- iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
+ iop = InstObjParams(name, Name, 'FPCompareOp', code)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index 654dd8921..2f131f6d9 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -224,7 +224,7 @@ output decoder {{
}};
def format IntOp(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'IntOp', CodeBlock(code), opt_flags)
+ iop = InstObjParams(name, Name, 'IntOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = RegNopCheckDecode.subst(iop)
@@ -232,7 +232,7 @@ def format IntOp(code, *opt_flags) {{
}};
def format IntImmOp(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'IntImmOp', CodeBlock(code), opt_flags)
+ iop = InstObjParams(name, Name, 'IntImmOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = ImmNopCheckDecode.subst(iop)
@@ -240,15 +240,10 @@ def format IntImmOp(code, *opt_flags) {{
}};
def format HiLoOp(code, *opt_flags) {{
- if '.sd' in code:
- code = 'int64_t ' + code
- elif '.ud' in code:
- code = 'uint64_t ' + code
-
code += 'HI = val<63:32>;\n'
code += 'LO = val<31:0>;\n'
- iop = InstObjParams(name, Name, 'HiLoOp', CodeBlock(code), opt_flags)
+ iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@@ -256,11 +251,11 @@ def format HiLoOp(code, *opt_flags) {{
}};
def format HiLoMiscOp(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'HiLoMiscOp', CodeBlock(code), opt_flags)
+ iop = InstObjParams(name, Name, 'HiLoMiscOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = HiLoExecute.subst(iop)
+ exec_output = BasicExecute.subst(iop)
}};
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index e786cfbe2..fccda2775 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -166,22 +166,28 @@ def template CompleteAccDeclare {{
}};
-def template LoadStoreConstructor {{
+def template EACompConstructor {{
/** TODO: change op_class to AddrGenOp or something (requires
* creating new member of OpClass enum in op_class.hh, updating
* config files, etc.). */
inline %(class_name)s::EAComp::EAComp(MachInst machInst)
: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
{
- %(ea_constructor)s;
+ %(constructor)s;
}
+}};
+
+def template MemAccConstructor {{
inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
{
- %(memacc_constructor)s;
+ %(constructor)s;
}
+}};
+
+def template LoadStoreConstructor {{
inline %(class_name)s::%(class_name)s(MachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
new EAComp(machInst), new MemAcc(machInst))
@@ -202,7 +208,7 @@ def template EACompExecute {{
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
- %(code)s;
+ %(ea_code)s;
if (fault == NoFault) {
%(op_wb)s;
@@ -228,7 +234,7 @@ def template LoadMemAccExecute {{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
- %(code)s;
+ %(memacc_code)s;
}
if (fault == NoFault) {
@@ -327,7 +333,7 @@ def template StoreMemAccExecute {{
EA = xc->getEA();
if (fault == NoFault) {
- %(code)s;
+ %(memacc_code)s;
}
if (fault == NoFault) {
@@ -471,7 +477,7 @@ def template MiscMemAccExecute {{
EA = xc->getEA();
if (fault == NoFault) {
- %(code)s;
+ %(memacc_code)s;
}
return NoFault;
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 96435f8c9..d7240335e 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -74,7 +74,7 @@ def template MTExecute {{
// Primary format for integer operate instructions:
def format MipsMT() {{
code = 'panic(\"Mips MT Is Currently Unimplemented.\");\n'
- iop = InstObjParams(name, Name, 'MT', CodeBlock(code))
+ iop = InstObjParams(name, Name, 'MT', code)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa
index 7f3d313ad..a8995d658 100644
--- a/src/arch/mips/isa/formats/noop.isa
+++ b/src/arch/mips/isa/formats/noop.isa
@@ -125,7 +125,7 @@ def template ImmNopCheckDecode {{
// Like BasicOperate format, but generates NOP if RC/FC == 31
def format BasicOperateWithNopCheck(code, *opt_args) {{
- iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code),
+ iop = InstObjParams(name, Name, 'MipsStaticInst', code,
opt_args)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa
index b974ccbed..dbfbb8ce1 100644
--- a/src/arch/mips/isa/formats/tlbop.isa
+++ b/src/arch/mips/isa/formats/tlbop.isa
@@ -70,9 +70,7 @@ def template TlbOpExecute {{
// Primary format for integer operate instructions:
def format TlbOp(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+ iop = InstObjParams(name, Name, 'MipsStaticInst', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
diff --git a/src/arch/mips/isa/formats/trap.isa b/src/arch/mips/isa/formats/trap.isa
index b9066f374..96d1167d2 100644
--- a/src/arch/mips/isa/formats/trap.isa
+++ b/src/arch/mips/isa/formats/trap.isa
@@ -73,7 +73,7 @@ def format Trap(code, *flags) {{
code = 'warn(\"'
code += 'Trap Exception Handler Is Currently Not Implemented.'
code += '\");'
- iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+ iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa
index 73164bc0d..ec524113d 100644
--- a/src/arch/mips/isa/formats/util.isa
+++ b/src/arch/mips/isa/formats/util.isa
@@ -40,63 +40,24 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
# add hook to get effective addresses into execution trace output.
ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
- # generate code block objects
- ea_cblk = CodeBlock(ea_code)
- memacc_cblk = CodeBlock(memacc_code)
- postacc_cblk = CodeBlock(postacc_code)
-
# Some CPU models execute the memory operation as an atomic unit,
# while others want to separate them into an effective address
# computation and a memory access operation. As a result, we need
# to generate three StaticInst objects. Note that the latter two
# are nested inside the larger "atomic" one.
- # generate InstObjParams for EAComp object
- ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
-
- # generate InstObjParams for MemAcc object
- memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
- # in the split execution model, the MemAcc portion is responsible
- # for the post-access code.
- memacc_iop.postacc_code = postacc_cblk.code
-
- # generate InstObjParams for InitiateAcc, CompleteAcc object
- # The code used depends on the template being used
- if (exec_template_base == 'Load'):
- initiateacc_cblk = CodeBlock(ea_code + memacc_code)
- completeacc_cblk = CodeBlock(memacc_code + postacc_code)
- elif (exec_template_base.startswith('Store')):
- initiateacc_cblk = CodeBlock(ea_code + memacc_code)
- completeacc_cblk = CodeBlock(postacc_code)
- else:
- initiateacc_cblk = ''
- completeacc_cblk = ''
-
- initiateacc_iop = InstObjParams(name, Name, base_class, initiateacc_cblk,
- inst_flags)
-
- completeacc_iop = InstObjParams(name, Name, base_class, completeacc_cblk,
- inst_flags)
-
- if (exec_template_base == 'Load'):
- initiateacc_iop.ea_code = ea_cblk.code
- initiateacc_iop.memacc_code = memacc_cblk.code
- completeacc_iop.memacc_code = memacc_cblk.code
- completeacc_iop.postacc_code = postacc_cblk.code
- elif (exec_template_base.startswith('Store')):
- initiateacc_iop.ea_code = ea_cblk.code
- initiateacc_iop.memacc_code = memacc_cblk.code
- completeacc_iop.postacc_code = postacc_cblk.code
-
- # generate InstObjParams for unified execution
- cblk = CodeBlock(ea_code + memacc_code + postacc_code)
- iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
-
- iop.ea_constructor = ea_cblk.constructor
- iop.ea_code = ea_cblk.code
- iop.memacc_constructor = memacc_cblk.constructor
- iop.memacc_code = memacc_cblk.code
- iop.postacc_code = postacc_cblk.code
+ # Generate InstObjParams for each of the three objects. Note that
+ # they differ only in the set of code objects contained (which in
+ # turn affects the object's overall operand list).
+ iop = InstObjParams(name, Name, base_class,
+ { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
+ inst_flags)
+ ea_iop = InstObjParams(name, Name, base_class,
+ { 'ea_code':ea_code },
+ inst_flags)
+ memacc_iop = InstObjParams(name, Name, base_class,
+ { 'memacc_code':memacc_code, 'postacc_code':postacc_code },
+ inst_flags)
if mem_flags:
s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
@@ -117,14 +78,19 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
# (header_output, decoder_output, decode_block, exec_output)
- return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
+ return (LoadStoreDeclare.subst(iop),
+ EACompConstructor.subst(ea_iop)
+ + MemAccConstructor.subst(memacc_iop)
+ + LoadStoreConstructor.subst(iop),
decode_template.subst(iop),
EACompExecute.subst(ea_iop)
+ memAccExecTemplate.subst(memacc_iop)
+ fullExecTemplate.subst(iop)
- + initiateAccTemplate.subst(initiateacc_iop)
- + completeAccTemplate.subst(completeacc_iop))
+ + initiateAccTemplate.subst(iop)
+ + completeAccTemplate.subst(iop))
}};
+
+
output header {{
std::string inst2string(MachInst machInst);
}};
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index dee883c4a..7b57b31f5 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -173,6 +173,11 @@ namespace MipsISA
}
};
+ static inline int flattenIntIndex(ThreadContext * tc, int reg)
+ {
+ return reg;
+ }
+
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/mips/remote_gdb.hh b/src/arch/mips/remote_gdb.hh
new file mode 100644
index 000000000..5886ab849
--- /dev/null
+++ b/src/arch/mips/remote_gdb.hh
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#ifndef __ARCH_MIPS_REMOTE_GDB_HH__
+#define __ARCH_MIPS_REMOTE_GDB_HH__
+
+#include "base/remote_gdb.hh"
+
+namespace MipsISA
+{
+ class RemoteGDB : public BaseRemoteGDB
+ {
+ public:
+ //These needs to be written to suit MIPS
+
+ RemoteGDB(System *system, ThreadContext *context)
+ : BaseRemoteGDB(system, context, 1)
+ {}
+
+ bool acc(Addr, size_t)
+ { panic("acc not implemented for MIPS!"); }
+
+ void getregs()
+ { panic("getregs not implemented for MIPS!"); }
+
+ void setregs()
+ { panic("setregs not implemented for MIPS!"); }
+
+ void clearSingleStep()
+ { panic("clearSingleStep not implemented for MIPS!"); }
+
+ void setSingleStep()
+ { panic("setSingleStep not implemented for MIPS!"); }
+ };
+}
+
+#endif /* __ARCH_ALPHA_REMOTE_GDB_H__ */
diff --git a/src/arch/mips/syscallreturn.hh b/src/arch/mips/syscallreturn.hh
index ef1093caf..47290b634 100644
--- a/src/arch/mips/syscallreturn.hh
+++ b/src/arch/mips/syscallreturn.hh
@@ -32,51 +32,22 @@
#ifndef __ARCH_MIPS_SYSCALLRETURN_HH__
#define __ARCH_MIPS_SYSCALLRETURN_HH__
-class SyscallReturn {
- public:
- template <class T>
- SyscallReturn(T v, bool s)
- {
- retval = (uint32_t)v;
- success = s;
- }
-
- template <class T>
- SyscallReturn(T v)
- {
- success = (v >= 0);
- retval = (uint32_t)v;
- }
-
- ~SyscallReturn() {}
-
- SyscallReturn& operator=(const SyscallReturn& s) {
- retval = s.retval;
- success = s.success;
- return *this;
- }
-
- bool successful() { return success; }
- uint64_t value() { return retval; }
-
-
- private:
- uint64_t retval;
- bool success;
-};
+#include "sim/syscallreturn.hh"
+#include "cpu/thread_context.hh"
namespace MipsISA
{
- static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
+ static inline void setSyscallReturn(SyscallReturn return_value,
+ ThreadContext *tc)
{
if (return_value.successful()) {
// no error
- regs->setIntReg(SyscallSuccessReg, 0);
- regs->setIntReg(ReturnValueReg1, return_value.value());
+ tc->setIntReg(SyscallSuccessReg, 0);
+ tc->setIntReg(ReturnValueReg1, return_value.value());
} else {
// got an error, return details
- regs->setIntReg(SyscallSuccessReg, (IntReg) -1);
- regs->setIntReg(ReturnValueReg1, -return_value.value());
+ tc->setIntReg(SyscallSuccessReg, (IntReg) -1);
+ tc->setIntReg(ReturnValueReg1, -return_value.value());
}
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-02 10:55:51 +0000