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-rw-r--r--src/arch/mips/MipsTLB.py9
1 files changed, 3 insertions, 6 deletions
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index 1d0244e22..0054acae5 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -39,19 +39,16 @@ class MipsTLB(SimObject):
class MipsDTB(MipsTLB):
type = 'MipsDTB'
- cxx_namespace = 'MipsISA'
- cxx_class = 'DTB'
+ cxx_class = 'MipsISA::DTB'
size = 64
class MipsITB(MipsTLB):
type = 'MipsITB'
- cxx_namespace = 'MipsISA'
- cxx_class = 'ITB'
+ cxx_class = 'MipsISA::ITB'
size = 64
class MipsUTB(MipsTLB):
type = 'MipsUTB'
- cxx_namespace = 'MipsISA'
- cxx_class = 'UTB'
+ cxx_class = 'MipsISA::UTB'
size = 64