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-rw-r--r--src/arch/power/insts/branch.cc2
-rw-r--r--src/arch/power/insts/static_inst.cc18
2 files changed, 8 insertions, 12 deletions
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index f10e8453a..d13a0a7d3 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -153,7 +153,7 @@ BranchNonPCRelCond::generateDisassembly(Addr pc,
PowerISA::PCState
BranchRegCond::branchTarget(ThreadContext *tc) const
{
- uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].regIdx);
+ uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].index());
return regVal & 0xfffffffc;
}
diff --git a/src/arch/power/insts/static_inst.cc b/src/arch/power/insts/static_inst.cc
index 210205db2..85f9cf628 100644
--- a/src/arch/power/insts/static_inst.cc
+++ b/src/arch/power/insts/static_inst.cc
@@ -38,15 +38,12 @@ using namespace PowerISA;
void
PowerStaticInst::printReg(std::ostream &os, RegId reg) const
{
- switch (reg.regClass) {
- case IntRegClass:
- ccprintf(os, "r%d", reg.regIdx);
- break;
- case FloatRegClass:
- ccprintf(os, "f%d", reg.regIdx);
- break;
- case MiscRegClass:
- switch (reg.regIdx) {
+ if (reg.isIntReg())
+ ccprintf(os, "r%d", reg.index());
+ else if (reg.isFloatReg())
+ ccprintf(os, "f%d", reg.index());
+ else if (reg.isMiscReg())
+ switch (reg.index()) {
case 0: ccprintf(os, "cr"); break;
case 1: ccprintf(os, "xer"); break;
case 2: ccprintf(os, "lr"); break;
@@ -54,9 +51,8 @@ PowerStaticInst::printReg(std::ostream &os, RegId reg) const
default: ccprintf(os, "unknown_reg");
break;
}
- case CCRegClass:
+ else if (reg.isCCReg())
panic("printReg: POWER does not implement CCRegClass\n");
- }
}
std::string