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-rw-r--r--src/arch/power/insts/branch.cc2
-rw-r--r--src/arch/power/insts/static_inst.cc12
-rw-r--r--src/arch/power/insts/static_inst.hh2
3 files changed, 7 insertions, 9 deletions
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index f9876db8c..f10e8453a 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -153,7 +153,7 @@ BranchNonPCRelCond::generateDisassembly(Addr pc,
PowerISA::PCState
BranchRegCond::branchTarget(ThreadContext *tc) const
{
- uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1]);
+ uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].regIdx);
return regVal & 0xfffffffc;
}
diff --git a/src/arch/power/insts/static_inst.cc b/src/arch/power/insts/static_inst.cc
index db8c03002..210205db2 100644
--- a/src/arch/power/insts/static_inst.cc
+++ b/src/arch/power/insts/static_inst.cc
@@ -36,19 +36,17 @@
using namespace PowerISA;
void
-PowerStaticInst::printReg(std::ostream &os, int reg) const
+PowerStaticInst::printReg(std::ostream &os, RegId reg) const
{
- RegIndex rel_reg;
-
- switch (regIdxToClass(reg, &rel_reg)) {
+ switch (reg.regClass) {
case IntRegClass:
- ccprintf(os, "r%d", rel_reg);
+ ccprintf(os, "r%d", reg.regIdx);
break;
case FloatRegClass:
- ccprintf(os, "f%d", rel_reg);
+ ccprintf(os, "f%d", reg.regIdx);
break;
case MiscRegClass:
- switch (rel_reg) {
+ switch (reg.regIdx) {
case 0: ccprintf(os, "cr"); break;
case 1: ccprintf(os, "xer"); break;
case 2: ccprintf(os, "lr"); break;
diff --git a/src/arch/power/insts/static_inst.hh b/src/arch/power/insts/static_inst.hh
index 48e5fa94b..b7a818a2c 100644
--- a/src/arch/power/insts/static_inst.hh
+++ b/src/arch/power/insts/static_inst.hh
@@ -59,7 +59,7 @@ class PowerStaticInst : public StaticInst
/// Print a register name for disassembly given the unique
/// dependence tag number (FP or int).
void
- printReg(std::ostream &os, int reg) const;
+ printReg(std::ostream &os, RegId reg) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;