diff options
Diffstat (limited to 'src/arch/power/isa')
| -rw-r--r-- | src/arch/power/isa/decoder.isa | 36 | ||||
| -rw-r--r-- | src/arch/power/isa/formats/branch.isa | 6 | ||||
| -rw-r--r-- | src/arch/power/isa/formats/unknown.isa | 2 | ||||
| -rw-r--r-- | src/arch/power/isa/operands.isa | 3 |
4 files changed, 35 insertions, 12 deletions
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 3252ff14a..671f57389 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -381,12 +381,20 @@ decode OPCODE default Unknown::unknown() { // Conditionally branch relative to PC based on CR and CTR. format BranchPCRelCondCtr { - 0: bc({{ NPC = PC + disp; }}); + 0: bc({{ + PowerISA::PCState pc = PCS; + pc.npc((uint32_t)(pc.pc() + disp)); + PCS = pc; + }}); } // Conditionally branch to fixed address based on CR and CTR. format BranchNonPCRelCondCtr { - 1: bca({{ NPC = targetAddr; }}); + 1: bca({{ + PowerISA::PCState pc = PCS; + pc.npc(targetAddr); + PCS = pc; + }}); } } @@ -394,12 +402,20 @@ decode OPCODE default Unknown::unknown() { // Unconditionally branch relative to PC. format BranchPCRel { - 0: b({{ NPC = PC + disp; }}); + 0: b({{ + PowerISA::PCState pc = PCS; + pc.npc((uint32_t)(pc.pc() + disp)); + PCS = pc; + }}); } // Unconditionally branch to fixed address. format BranchNonPCRel { - 1: ba({{ NPC = targetAddr; }}); + 1: ba({{ + PowerISA::PCState pc = PCS; + pc.npc(targetAddr); + PCS = pc; + }}); } } @@ -407,12 +423,20 @@ decode OPCODE default Unknown::unknown() { // Conditionally branch to address in LR based on CR and CTR. format BranchLrCondCtr { - 16: bclr({{ NPC = LR & 0xfffffffc; }}); + 16: bclr({{ + PowerISA::PCState pc = PCS; + pc.npc(LR & 0xfffffffc); + PCS = pc; + }}); } // Conditionally branch to address in CTR based on CR. format BranchCtrCond { - 528: bcctr({{ NPC = CTR & 0xfffffffc; }}); + 528: bcctr({{ + PowerISA::PCState pc = PCS; + pc.npc(CTR & 0xfffffffc); + PCS = pc; + }}); } // Condition register manipulation instructions. diff --git a/src/arch/power/isa/formats/branch.isa b/src/arch/power/isa/formats/branch.isa index d51ed5c25..da1579ea8 100644 --- a/src/arch/power/isa/formats/branch.isa +++ b/src/arch/power/isa/formats/branch.isa @@ -48,7 +48,7 @@ let {{ # Simple code to update link register (LR). -updateLrCode = 'LR = PC + 4;' +updateLrCode = 'PowerISA::PCState lrpc = PCS; LR = lrpc.pc() + 4;' }}; @@ -105,7 +105,7 @@ def GetCondCode(br_code): cond_code = 'if(condOk(CR)) {\n' cond_code += ' ' + br_code + '\n' cond_code += '} else {\n' - cond_code += ' NPC = NPC;\n' + cond_code += ' PCS = PCS;\n' cond_code += '}\n' return cond_code @@ -119,7 +119,7 @@ def GetCtrCondCode(br_code): cond_code += 'if(ctr_ok && cond_ok) {\n' cond_code += ' ' + br_code + '\n' cond_code += '} else {\n' - cond_code += ' NPC = NPC;\n' + cond_code += ' PCS = PCS;\n' cond_code += '}\n' cond_code += 'CTR = ctr;\n' return cond_code diff --git a/src/arch/power/isa/formats/unknown.isa b/src/arch/power/isa/formats/unknown.isa index 06e6ece26..8914cf9a6 100644 --- a/src/arch/power/isa/formats/unknown.isa +++ b/src/arch/power/isa/formats/unknown.isa @@ -76,7 +76,7 @@ output exec {{ { panic("attempt to execute unknown instruction at %#x" "(inst 0x%08x, opcode 0x%x, binary: %s)", - xc->readPC(), machInst, OPCODE, inst2string(machInst)); + xc->pcState().pc(), machInst, OPCODE, inst2string(machInst)); return new UnimplementedOpcodeFault; } }}; diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa index fc6c32685..908e6e0e7 100644 --- a/src/arch/power/isa/operands.isa +++ b/src/arch/power/isa/operands.isa @@ -59,8 +59,7 @@ def operands {{ 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8), # Program counter and next - 'PC': ('PC', 'uw', None, (None, None, 'IsControl'), 9), - 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9), + 'PCS': ('PCState', 'uq', None, (None, None, 'IsControl'), 9), # Control registers 'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9), |